mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-25 00:33:15 +00:00
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
c85e832eb7
commit
ee568cf794
@ -524,8 +524,8 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
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return true;
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}
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/// getDefaultPred - Returns a ARMCC::AL immediate node.
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static inline SDOperand getDefaultPred(SelectionDAG *CurDAG) {
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/// getAL - Returns a ARMCC::AL immediate node.
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static inline SDOperand getAL(SelectionDAG *CurDAG) {
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return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
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}
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@ -564,10 +564,11 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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CPIdx,
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CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(0, MVT::i32),
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getDefaultPred(CurDAG),
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getAL(CurDAG),
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CurDAG->getRegister(0, MVT::i32),
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CurDAG->getEntryNode()
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};
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ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 5);
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ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
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}
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ReplaceUses(Op, SDOperand(ResNode, 0));
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return NULL;
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@ -583,10 +584,11 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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if (Subtarget->isThumb())
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return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
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CurDAG->getTargetConstant(0, MVT::i32));
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else
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return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, TFI,
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CurDAG->getTargetConstant(0, MVT::i32),
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getDefaultPred(CurDAG));
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else {
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SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 4);
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}
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}
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case ISD::ADD: {
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// Select add sp, c to tADDhirr.
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@ -617,9 +619,10 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
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SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(ShImm, MVT::i32),
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getDefaultPred(CurDAG)
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32)
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};
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return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 5);
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return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 6);
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}
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if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
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SDOperand V = Op.getOperand(0);
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@ -627,28 +630,31 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
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SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(ShImm, MVT::i32),
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getDefaultPred(CurDAG)
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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};
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return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 5);
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return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 6);
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}
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}
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break;
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case ARMISD::FMRRD:
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AddToISelQueue(Op.getOperand(0));
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return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
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Op.getOperand(0), getDefaultPred(CurDAG));
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case ARMISD::MULHILOU:
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Op.getOperand(0), getAL(CurDAG),
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CurDAG->getRegister(0, MVT::i32));
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case ARMISD::MULHILOU: {
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AddToISelQueue(Op.getOperand(0));
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AddToISelQueue(Op.getOperand(1));
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return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32,
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Op.getOperand(0), Op.getOperand(1),
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getDefaultPred(CurDAG));
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case ARMISD::MULHILOS:
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SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 4);
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}
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case ARMISD::MULHILOS: {
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AddToISelQueue(Op.getOperand(0));
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AddToISelQueue(Op.getOperand(1));
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return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32,
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Op.getOperand(0), Op.getOperand(1),
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getDefaultPred(CurDAG));
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SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 4);
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}
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case ISD::LOAD: {
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LoadSDNode *LD = cast<LoadSDNode>(Op);
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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@ -688,16 +694,158 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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AddToISelQueue(Chain);
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AddToISelQueue(Base);
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AddToISelQueue(Offset);
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SDOperand Ops[]= { Base, Offset, AMOpc, getDefaultPred(CurDAG), Chain };
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SDOperand Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
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CurDAG->getRegister(0, MVT::i32), Chain };
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return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
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MVT::Other, Ops, 5);
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MVT::Other, Ops, 6);
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}
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}
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// Other cases are autogenerated.
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break;
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}
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}
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case ARMISD::BRCOND: {
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// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
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// Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 1 size = 0
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// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
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// Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 1 size = 0
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unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
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SDOperand Chain = Op.getOperand(0);
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SDOperand N1 = Op.getOperand(1);
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SDOperand N2 = Op.getOperand(2);
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SDOperand N3 = Op.getOperand(3);
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SDOperand InFlag = Op.getOperand(4);
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assert(N1.getOpcode() == ISD::BasicBlock);
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assert(N2.getOpcode() == ISD::Constant);
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assert(N3.getOpcode() == ISD::Register);
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AddToISelQueue(Chain);
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AddToISelQueue(N1);
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AddToISelQueue(InFlag);
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SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
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SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag };
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SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
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Chain = SDOperand(ResNode, 0);
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InFlag = SDOperand(ResNode, 1);
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ReplaceUses(SDOperand(Op.Val, 1), InFlag);
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ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo));
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return NULL;
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}
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case ARMISD::CMOV: {
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bool isThumb = Subtarget->isThumb();
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MVT::ValueType VT = Op.getValueType();
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SDOperand N0 = Op.getOperand(0);
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SDOperand N1 = Op.getOperand(1);
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SDOperand N2 = Op.getOperand(2);
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SDOperand N3 = Op.getOperand(3);
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SDOperand InFlag = Op.getOperand(4);
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assert(N2.getOpcode() == ISD::Constant);
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assert(N3.getOpcode() == ISD::Register);
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// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 18 cost = 1 size = 0
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SDOperand CPTmp0;
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SDOperand CPTmp1;
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SDOperand CPTmp2;
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if (!isThumb && VT == MVT::i32 &&
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SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
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AddToISelQueue(N0);
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AddToISelQueue(CPTmp0);
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AddToISelQueue(CPTmp1);
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AddToISelQueue(CPTmp2);
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AddToISelQueue(InFlag);
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SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
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SDOperand Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false,
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// (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
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// (imm:i32):$cc)
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// Emits: (MOVCCi:i32 GPR:i32:$false,
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// (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
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// Pattern complexity = 10 cost = 1 size = 0
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if (VT == MVT::i32 &&
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N3.getOpcode() == ISD::Constant &&
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Predicate_so_imm(N3.Val)) {
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AddToISelQueue(N0);
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AddToISelQueue(InFlag);
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SDOperand Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
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Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
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SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
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SDOperand Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 1 size = 0
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//
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 11 size = 0
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//
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// Also FCPYScc and FCPYDcc.
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AddToISelQueue(N0);
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AddToISelQueue(N1);
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AddToISelQueue(InFlag);
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SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
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SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
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unsigned Opc = 0;
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switch (VT) {
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default: assert(false && "Illegal conditional move type!");
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break;
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case MVT::i32:
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Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
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break;
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case MVT::f32:
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Opc = ARM::FCPYScc;
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break;
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case MVT::f64:
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Opc = ARM::FCPYDcc;
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break;
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}
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return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
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}
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case ARMISD::CNEG: {
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MVT::ValueType VT = Op.getValueType();
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SDOperand N0 = Op.getOperand(0);
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SDOperand N1 = Op.getOperand(1);
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SDOperand N2 = Op.getOperand(2);
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SDOperand N3 = Op.getOperand(3);
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SDOperand InFlag = Op.getOperand(4);
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assert(N2.getOpcode() == ISD::Constant);
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assert(N3.getOpcode() == ISD::Register);
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AddToISelQueue(N0);
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AddToISelQueue(N1);
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AddToISelQueue(InFlag);
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SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
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SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
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unsigned Opc = 0;
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switch (VT) {
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default: assert(false && "Illegal conditional move type!");
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break;
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case MVT::f32:
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Opc = ARM::FNEGScc;
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break;
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case MVT::f64:
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Opc = ARM::FNEGDcc;
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break;
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}
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return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
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}
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}
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return SelectCode(Op);
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}
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