From eececbab32fe072f7d6b31786787dfea270b2dbb Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sun, 25 Dec 2005 17:36:48 +0000 Subject: [PATCH] add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25011 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaAsmPrinter.cpp | 6 +++--- lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 23 ++++++++++++++--------- lib/Target/Alpha/AlphaISelPattern.cpp | 15 ++++++++------- lib/Target/Alpha/AlphaInstrFormats.td | 9 ++++++--- lib/Target/Alpha/AlphaInstrInfo.td | 17 +++++++---------- 5 files changed, 38 insertions(+), 32 deletions(-) diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp index 59b9199b920..29627c518d9 100644 --- a/lib/Target/Alpha/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp @@ -136,9 +136,9 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { case MachineOperand::MO_GlobalAddress: //Abuse PCrel to specify pcrel calls //calls are the only thing that use this flag - if (MO.isPCRelative()) - O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng"; - else +// if (MO.isPCRelative()) +// O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng"; +// else O << Mang->getValueName(MO.getGlobal()); return; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 5fadc81ce84..e51db4127de 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -194,9 +194,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) { CurDAG->getBasicBlock(Dest), Chain); } - case ISD::BR: - return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1), - Select(N->getOperand(0))); case ISD::FrameIndex: { int FI = cast(N)->getIndex(); return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, @@ -214,7 +211,7 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) { Chain.getValue(1)); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)), Chain.getValue(1)); - Chain = CurDAG->getTargetNode(Alpha::JSRsDAG, MVT::Other, MVT::Flag, + Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, Chain.getValue(1)); @@ -359,7 +356,7 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { SDNode *N = Op.Val; SDOperand Chain = Select(N->getOperand(0)); - SDOperand Addr = Select(N->getOperand(1)); + SDOperand Addr = N->getOperand(1); SDOperand InFlag; // Null incoming flag value. std::vector CallOperands; @@ -404,12 +401,20 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { } - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); - InFlag = Chain.getValue(1); // Finally, once everything is in registers to pass to the call, emit the // call itself. - Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, MVT::Flag, - Chain, InFlag ); + if (Addr.getOpcode() == AlphaISD::GPRelLo) { + SDOperand GOT = getGlobalBaseReg(); + Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); + InFlag = Chain.getValue(1); + Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, + Addr.getOperand(0), Chain, InFlag); + } else { + Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Addr), InFlag); + InFlag = Chain.getValue(1); + Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, + Chain, InFlag ); + } InFlag = Chain.getValue(1); std::vector CallResults; diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index afacf726cb3..92f16e8f7f3 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -824,17 +824,18 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { } } //build the right kind of call - GlobalAddressSDNode *GASD = dyn_cast(N.getOperand(1)); - if (GASD && !GASD->getGlobal()->isExternal()) { + if (N.getOperand(1).getOpcode() == AlphaISD::GPRelLo) { //use PC relative branch call AlphaLowering.restoreGP(BB); - BuildMI(BB, Alpha::BSR, 1, Alpha::R26) - .addGlobalAddress(GASD->getGlobal(),true); + BuildMI(BB, Alpha::BSR, 1) + .addGlobalAddress(cast(N.getOperand(1) + .getOperand(0)) + ->getGlobal(),true); } else { //no need to restore GP as we are doing an indirect call Tmp1 = SelectExpr(N.getOperand(1)); BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1); - BuildMI(BB, Alpha::JSR, 2, Alpha::R26).addReg(Alpha::R27).addImm(0); + BuildMI(BB, Alpha::JSR, 0); } //push the result into a virtual register @@ -1237,7 +1238,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp2).addReg(Tmp2); BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp3).addReg(Tmp3); BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1); - BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0); + BuildMI(BB, Alpha::JSRs, 0); BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27); return Result; @@ -1551,7 +1552,7 @@ void AlphaISel::Select(SDOperand N) { cast(N.getOperand(1))->getBasicBlock(); Select(N.getOperand(0)); - BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest); + BuildMI(BB, Alpha::BR, 1).addMBB(Dest); return; } diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index 011b28fcba3..85afcd2b2c9 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -95,10 +95,13 @@ class BForm opcode, string asmstr> let Inst{25-21} = Ra; let Inst{20-0} = disp; } +def target : Operand {} let isBranch = 1, isTerminator = 1 in -class BFormD opcode, string asmstr> - : InstAlpha { - bits<5> Ra = 31; +class BFormD opcode, string asmstr, list pattern> + : InstAlpha { + let Pattern = pattern; + + bits<5> Ra; bits<21> disp; let Inst{25-21} = Ra; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index d73c3abab8c..939456fef08 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -411,14 +411,13 @@ let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1">; //Return from subroutine def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump -let isCall = 1, +let isCall = 1, Ra = 26, Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, - R20, R21, R22, R23, R24, R25, R27, R28, R29, + R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, F0, F1, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in { - def JSR : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine - def BSR : BForm<0x34, "bsr $RA,$DISP">; //Branch to subroutine + def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", []>; //Branch to subroutine } let isCall = 1, Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, @@ -426,19 +425,17 @@ let isCall = 1, F0, F1, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in { - def JSRDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine + def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine } -let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in - def JSRs : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem let isCall = 1, Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in - def JSRsDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0">; //Jump to div or rem + def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0">; //Jump to div or rem def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return -def BR : BForm<0x30, "br $RA,$DISP">; //Branch -def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch +let Ra = 31 in +def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>; let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {