Change llc command line for register allocators

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8815 91177308-0d34-0410-b5e6-96231b3b80d8

docs/CommandGuide/llc.html

@@ -95,11 +95,6 @@ OPTIONS
 	Disable frame pointer elimination optimization.
 	<p>
 
-	<li>-disable-local-ra    
-	<br>
-	Use Simple RA instead of Local RegAlloc.
-	<p>
-
 	<li>-disable-pattern-isel
 	<br>
 	Use the 'simple' X86 instruction selector.
@@ -146,13 +141,11 @@ OPTIONS
 	architectures are:
 
 	<dl compact>
-		<di> x86               
-		<dd>
-		IA-32 (Pentium and above)
-		<p>
+		<di> x86
+		<dd>IA-32 (Pentium and above)</dd>
 
-		<di> sparc             
-		<dd>SPARC V9
+		<di> sparc
+		<dd>SPARC V9</dd>
 	</dl>
 	<p>
 
@@ -166,6 +159,19 @@ OPTIONS
 	Print generated machine code.
 	<p>
 
+	<li>-regalloc=&lt;ra&gt;
+	<br>
+        Specify the register allocator to use. The default is <i>simple<i>.
+        Valid register allocators are:
+	<dl compact>
+		<di> simple
+		<dd>Very simple register allocator</dd>
+
+		<di> local
+		<dd>Local register allocator</dd>
+	</dl>
+	<p>
+
 	<li> -help
 	<br>
 	Print a summary of command line options.

include/llvm/CodeGen/Passes.h

@@ -19,6 +19,8 @@ class TargetMachine;
 //
 extern const PassInfo *PHIEliminationID;
 
+enum RegAllocName { simple, local };
+
 /// SimpleRegisterAllocation Pass - This pass converts the input machine code
 /// from SSA form to use explicit registers by spilling every register.  Wow,
 /// great policy huh?

lib/Target/X86/X86TargetMachine.cpp

@@ -16,8 +16,15 @@
 #include "Support/Statistic.h"
 
 namespace {
-  cl::opt<bool> NoLocalRA("disable-local-ra",
-                          cl::desc("Use Simple RA instead of Local RegAlloc"));
+  cl::opt<RegAllocName>
+  RegAlloc("regalloc",
+           cl::desc("Register allocator to use: (default = simple)"),
+           cl::Prefix,
+           cl::values(clEnumVal(simple, "  simple register allocator"),
+                      clEnumVal(local,  "  local register allocator"),
+                      0),
+           cl::init(local));
+
   cl::opt<bool> PrintCode("print-machineinstrs",
 			  cl::desc("Print generated machine code"));
   cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
@@ -66,10 +73,16 @@ bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
     PM.add(createMachineFunctionPrinterPass());
 
   // Perform register allocation to convert to a concrete x86 representation
-  if (NoLocalRA)
+  switch (RegAlloc) {
+  case simple:
     PM.add(createSimpleRegisterAllocator());
-  else
+    break;
+  case local:
     PM.add(createLocalRegisterAllocator());
+    break;
+  default:
+    assert(0 && "no register allocator selected");
+  }
 
   if (PrintCode)
     PM.add(createMachineFunctionPrinterPass());
@@ -113,10 +126,16 @@ bool X86TargetMachine::addPassesToJITCompile(FunctionPassManager &PM) {
     PM.add(createMachineFunctionPrinterPass());
 
   // Perform register allocation to convert to a concrete x86 representation
-  if (NoLocalRA)
+  switch (RegAlloc) {
+  case simple:
     PM.add(createSimpleRegisterAllocator());
-  else
+    break;
+  case local:
     PM.add(createLocalRegisterAllocator());
+    break;
+  default:
+    assert(0 && "no register allocator selected");
+  }
 
   if (PrintCode)
     PM.add(createMachineFunctionPrinterPass());

test/CodeGen/X86/2002-12-23-LocalRAProblem.llx

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | lli -force-interpreter=false -disable-local-ra=false
+; RUN: llvm-as < %s | lli -force-interpreter=false -regalloc=simple
 ;-print-machineinstrs 
 
 int %main() {

test/CodeGen/X86/2002-12-23-SubProblem.llx

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | lli -force-interpreter=false -disable-local-ra
+; RUN: llvm-as < %s | lli -force-interpreter=false -regalloc=simple
 
 int %main(int %B) {
 	;%B = add int 0, 1