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https://github.com/c64scene-ar/llvm-6502.git
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X86: lower ATOMIC_CMP_SWAP_WITH_SUCCESS directly
Lowering this new node allows us to fold the almost universal comparison for success before it's even formed. Instead we can create a copy from EFLAGS and an X86ISD::SETCC operation since all "cmpxchg" instructions set the zero-flag to the correct value. rdar://problem/13201607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210923 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
f317d86f8f
commit
eee7a7a836
@ -580,7 +580,7 @@ void X86TargetLowering::resetOperationActions() {
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// Expand certain atomics
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for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
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MVT VT = IntVTs[i];
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setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
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setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
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}
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@ -601,7 +601,7 @@ void X86TargetLowering::resetOperationActions() {
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}
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if (Subtarget->hasCmpxchg16b()) {
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
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}
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// FIXME - use subtarget debug flags
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@ -14529,7 +14529,7 @@ static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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break;
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}
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SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
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Op.getOperand(2), SDValue());
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Op.getOperand(2), SDValue());
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SDValue Ops[] = { cpIn.getValue(0),
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Op.getOperand(1),
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Op.getOperand(3),
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@ -14539,9 +14539,18 @@ static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
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SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
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Ops, T, MMO);
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SDValue cpOut =
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DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
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return cpOut;
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SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
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MVT::i32, cpOut.getValue(2));
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SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
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DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
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DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
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DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
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DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
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return SDValue();
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}
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static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
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@ -14721,7 +14730,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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default: llvm_unreachable("Should not custom lower this!");
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
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case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
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case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
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return LowerCMP_SWAP(Op, Subtarget, DAG);
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case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
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case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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@ -14803,8 +14813,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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}
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static void ReplaceATOMIC_LOAD(SDNode *Node,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) {
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) {
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SDLoc dl(Node);
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EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
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@ -14813,16 +14823,16 @@ static void ReplaceATOMIC_LOAD(SDNode *Node,
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// (The only way to get a 16-byte load is cmpxchg16b)
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// FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
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SDValue Zero = DAG.getConstant(0, VT);
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SDVTList VTs = DAG.getVTList(VT, MVT::Other);
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SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
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SDValue Swap =
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DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP, dl, VT, VTs,
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DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
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Node->getOperand(0), Node->getOperand(1), Zero, Zero,
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cast<AtomicSDNode>(Node)->getMemOperand(),
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cast<AtomicSDNode>(Node)->getOrdering(),
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cast<AtomicSDNode>(Node)->getOrdering(),
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cast<AtomicSDNode>(Node)->getSynchScope());
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Results.push_back(Swap.getValue(0));
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Results.push_back(Swap.getValue(1));
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Results.push_back(Swap.getValue(2));
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}
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static void
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@ -14938,7 +14948,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
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Results);
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}
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case ISD::ATOMIC_CMP_SWAP: {
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case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
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EVT T = N->getValueType(0);
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assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
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bool Regs64bit = T == MVT::i128;
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@ -14980,8 +14990,17 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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Regs64bit ? X86::RDX : X86::EDX,
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HalfT, cpOutL.getValue(2));
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SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
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SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
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MVT::i32, cpOutH.getValue(2));
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SDValue Success =
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DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
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Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
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Results.push_back(cpOutH.getValue(1));
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Results.push_back(Success);
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Results.push_back(EFLAGS.getValue(1));
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return;
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}
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case ISD::ATOMIC_LOAD_ADD:
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87
test/CodeGen/X86/cmpxchg-i1.ll
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87
test/CodeGen/X86/cmpxchg-i1.ll
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@ -0,0 +1,87 @@
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; RUN: llc -mtriple=x86_64 -o - %s | FileCheck %s
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define i1 @try_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: try_cmpxchg:
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; CHECK: cmpxchgl
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; CHECK-NOT: cmp
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; CHECK: sete %al
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; CHECK: retq
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%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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ret i1 %success
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}
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define void @cmpxchg_flow(i64* %addr, i64 %desired, i64 %new) {
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; CHECK-LABEL: cmpxchg_flow:
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; CHECK: cmpxchgq
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; CHECK-NOT: cmp
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; CHECK-NOT: set
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; CHECK: {{jne|jeq}}
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%pair = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst seq_cst
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%success = extractvalue { i64, i1 } %pair, 1
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br i1 %success, label %true, label %false
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true:
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call void @foo()
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ret void
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false:
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call void @bar()
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ret void
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}
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define i64 @cmpxchg_sext(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: cmpxchg_sext:
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; CHECK-DAG: cmpxchgl
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; CHECK-NOT: cmpl
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; CHECK: sete %al
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; CHECK: retq
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%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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%mask = sext i1 %success to i64
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ret i64 %mask
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}
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define i32 @cmpxchg_zext(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: cmpxchg_zext:
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; CHECK: cmpxchgl
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; CHECK-NOT: cmp
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; CHECK: sete [[BYTE:%[a-z0-9]+]]
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; CHECK: movzbl [[BYTE]], %eax
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%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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%mask = zext i1 %success to i32
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ret i32 %mask
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}
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define i32 @cmpxchg_use_eflags_and_val(i32* %addr, i32 %offset) {
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; CHECK-LABEL: cmpxchg_use_eflags_and_val:
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; CHECK: movl (%rdi), %e[[OLDVAL:[a-z0-9]+]]
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; CHECK: [[LOOPBB:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: leal (%r[[OLDVAL]],%rsi), [[NEW:%[a-z0-9]+]]
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; CHECK: cmpxchgl [[NEW]], (%rdi)
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; CHECK-NOT: cmpl
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; CHECK: jne [[LOOPBB]]
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; Result already in %eax
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; CHECK: retq
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entry:
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%init = load atomic i32* %addr seq_cst, align 4
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br label %loop
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loop:
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%old = phi i32 [%init, %entry], [%oldval, %loop]
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%new = add i32 %old, %offset
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%pair = cmpxchg i32* %addr, i32 %old, i32 %new seq_cst seq_cst
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%oldval = extractvalue { i32, i1 } %pair, 0
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%success = extractvalue { i32, i1 } %pair, 1
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br i1 %success, label %done, label %loop
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done:
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ret i32 %oldval
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}
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declare void @foo()
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declare void @bar()
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83
test/CodeGen/X86/cmpxchg-i128-i1.ll
Normal file
83
test/CodeGen/X86/cmpxchg-i128-i1.ll
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@ -0,0 +1,83 @@
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; RUN: llc -mcpu=core-avx2 -mtriple=x86_64 -o - %s | FileCheck %s
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define i1 @try_cmpxchg(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: try_cmpxchg:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmp
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; CHECK: sete %al
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; CHECK: retq
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%success = extractvalue { i128, i1 } %pair, 1
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ret i1 %success
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}
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define void @cmpxchg_flow(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: cmpxchg_flow:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmp
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; CHECK-NOT: set
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; CHECK: {{jne|jeq}}
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%success = extractvalue { i128, i1 } %pair, 1
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br i1 %success, label %true, label %false
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true:
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call void @foo()
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ret void
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false:
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call void @bar()
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ret void
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}
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; Can't use the flags here because cmpxchg16b only sets ZF.
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define i1 @cmpxchg_arithcmp(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: cmpxchg_arithcmp:
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; CHECK: cmpxchg16b
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; CHECK: cmpq
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; CHECK: retq
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%oldval = extractvalue { i128, i1 } %pair, 0
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%success = icmp sge i128 %oldval, %desired
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ret i1 %success
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}
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define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: cmpxchg_zext:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmpq
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; CHECK: sete [[BYTE:%[a-z0-9]+]]
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; CHECK: movzbl [[BYTE]], %eax
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%success = extractvalue { i128, i1 } %pair, 1
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%mask = zext i1 %success to i128
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ret i128 %mask
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}
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define i128 @cmpxchg_use_eflags_and_val(i128* %addr, i128 %offset) {
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; CHECK-LABEL: cmpxchg_use_eflags_and_val:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmpq
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; CHECK: jne
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entry:
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%init = load atomic i128* %addr seq_cst, align 16
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br label %loop
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loop:
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%old = phi i128 [%init, %entry], [%oldval, %loop]
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%new = add i128 %old, %offset
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%pair = cmpxchg i128* %addr, i128 %old, i128 %new seq_cst seq_cst
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%oldval = extractvalue { i128, i1 } %pair, 0
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%success = extractvalue { i128, i1 } %pair, 1
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br i1 %success, label %done, label %loop
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done:
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ret i128 %old
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}
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declare void @foo()
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declare void @bar()
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