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https://github.com/c64scene-ar/llvm-6502.git
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Arranged stack frame - needs furhter organization
Moved InsertCallerSaveInstr to the SparcRegInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1106 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
parent
fca59d7dc9
commit
ef1b0cb9a5
@ -22,7 +22,7 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
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Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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AddedInstrMap(), StackOffsets()
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AddedInstrMap(), StackOffsets(), PhiInstList()
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{
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// **TODO: use an actual reserved color list
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@ -227,7 +227,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *const MInst = *MInstIterator;
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const MachineInstr * MInst = *MInstIterator;
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// get the LV set after the instruction
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const LiveVarSet *const LVSetAI =
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@ -268,6 +268,12 @@ void PhyRegAlloc::buildInterferenceGraphs()
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addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
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}
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// record phi instrns in PhiInstList
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if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
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PhiInstList.push_back( MInst );
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} // for all machine instructions in BB
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} // for all BBs in method
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@ -1115,6 +1121,53 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs()
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void PhyRegAlloc::insertPhiEleminateInstrns() {
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vector< const MachineInstr *>:: const_iterator It = PhiInstList.begin();
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for( ; It != PhiInstList.end(); ++It ) {
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const MachineInstr *PhiMI = *It;
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Value *Def = (PhiMI->getOperand(0)).getVRegValue();
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const LiveRange *LROfDef = LRI.getLiveRangeForValue( Def );
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assert(LROfDef && "NO LR for a def of phi");
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for(unsigned OpNum=1; OpNum < PhiMI->getNumOperands(); ++OpNum) {
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if( OpNum % 2) { // i.e., the
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Value *Use = (PhiMI->getOperand(OpNum)).getVRegValue();
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const LiveRange *LROfUse = LRI.getLiveRangeForValue( Use );
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if( LROfUse != LROfDef) {
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// the result of the phi received a live range different to
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// that of this use, so copy it
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const BasicBlock *BB =
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(BasicBlock *) (PhiMI->getOperand(OpNum+1)).getVRegValue();
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MachineCodeForBasicBlock& MIVec = (BB)->getMachineInstrVec();
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MachineInstr *AdI = MRI.cpValue2Value(Use, Def);
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MIVec.push_back( AdI );
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cerr << "\n%%% Added a phi elimination instr: " << *AdI;
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} // if LRs are different
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} // if operand is an incoming Value (i.e., not a BB)
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} // for all phi operands
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} // for all phi instrns in PhiInstMap
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}
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//----------------------------------------------------------------------------
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@ -1150,6 +1203,10 @@ void PhyRegAlloc::allocateRegisters()
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LRI.coalesceLRs(); // coalesce all live ranges
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// coalscing could not get rid of all phi's, add phi elimination
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// instructions
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// insertPhiEleminateInstrns();
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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@ -22,7 +22,7 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
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Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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AddedInstrMap(), StackOffsets()
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AddedInstrMap(), StackOffsets(), PhiInstList()
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{
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// **TODO: use an actual reserved color list
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@ -227,7 +227,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *const MInst = *MInstIterator;
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const MachineInstr * MInst = *MInstIterator;
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// get the LV set after the instruction
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const LiveVarSet *const LVSetAI =
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@ -268,6 +268,12 @@ void PhyRegAlloc::buildInterferenceGraphs()
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addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
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}
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// record phi instrns in PhiInstList
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if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
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PhiInstList.push_back( MInst );
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} // for all machine instructions in BB
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} // for all BBs in method
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@ -1115,6 +1121,53 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs()
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void PhyRegAlloc::insertPhiEleminateInstrns() {
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vector< const MachineInstr *>:: const_iterator It = PhiInstList.begin();
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for( ; It != PhiInstList.end(); ++It ) {
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const MachineInstr *PhiMI = *It;
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Value *Def = (PhiMI->getOperand(0)).getVRegValue();
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const LiveRange *LROfDef = LRI.getLiveRangeForValue( Def );
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assert(LROfDef && "NO LR for a def of phi");
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for(unsigned OpNum=1; OpNum < PhiMI->getNumOperands(); ++OpNum) {
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if( OpNum % 2) { // i.e., the
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Value *Use = (PhiMI->getOperand(OpNum)).getVRegValue();
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const LiveRange *LROfUse = LRI.getLiveRangeForValue( Use );
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if( LROfUse != LROfDef) {
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// the result of the phi received a live range different to
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// that of this use, so copy it
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const BasicBlock *BB =
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(BasicBlock *) (PhiMI->getOperand(OpNum+1)).getVRegValue();
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MachineCodeForBasicBlock& MIVec = (BB)->getMachineInstrVec();
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MachineInstr *AdI = MRI.cpValue2Value(Use, Def);
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MIVec.push_back( AdI );
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cerr << "\n%%% Added a phi elimination instr: " << *AdI;
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} // if LRs are different
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} // if operand is an incoming Value (i.e., not a BB)
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} // for all phi operands
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} // for all phi instrns in PhiInstMap
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}
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//----------------------------------------------------------------------------
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@ -1150,6 +1203,10 @@ void PhyRegAlloc::allocateRegisters()
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LRI.coalesceLRs(); // coalesce all live ranges
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// coalscing could not get rid of all phi's, add phi elimination
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// instructions
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// insertPhiEleminateInstrns();
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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@ -401,6 +401,9 @@ class UltraSparcRegInfo : public MachineRegInfo
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MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
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const unsigned DestReg, const int RegType) const;
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MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
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inline bool isRegVolatile(const int RegClassID, const int Reg) const {
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return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
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}
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@ -979,7 +979,19 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
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}
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MachineInstr* UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
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MachineInstr * MI = NULL;
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MI = new MachineInstr(ADD, 3);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
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MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
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return MI;
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}
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