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[ARM] Add support for MVFR2 which is new in ARMv8

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov 2013-11-11 19:56:13 +00:00
parent 559d409633
commit ef572e31e2
5 changed files with 19 additions and 0 deletions
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2
lib/Target/ARM/ARMInstrVFP.td
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@ -1546,6 +1546,8 @@ let Uses = [FPSCR] in {
"vmrs", "\t$Rt, mvfr0", []>;
def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
"vmrs", "\t$Rt, mvfr1", []>;
def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
"vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
"vmrs", "\t$Rt, fpinst", []>;
def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),

1
lib/Target/ARM/ARMRegisterInfo.td
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@ -172,6 +172,7 @@ def ITSTATE : ARMReg<4, "itstate">;
// Special Registers - only available in privileged mode.
def FPSID : ARMReg<0, "fpsid">;
def MVFR2 : ARMReg<5, "mvfr2">;
def MVFR1 : ARMReg<6, "mvfr1">;
def MVFR0 : ARMReg<7, "mvfr0">;
def FPEXC : ARMReg<8, "fpexc">;

5
test/MC/ARM/fp-armv8.s
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@ -122,3 +122,8 @@
@ CHECK: vrintm.f64 d3, d4 @ encoding: [0x44,0x3b,0xbb,0xfe]
vrintm.f32 s12, s1
@ CHECK: vrintm.f32 s12, s1 @ encoding: [0x60,0x6a,0xbb,0xfe]
@ MVFR2
vmrs sp, mvfr2
@ CHECK: vmrs sp, mvfr2 @ encoding: [0x10,0xda,0xf5,0xee]

5
test/MC/Disassembler/ARM/fp-armv8.txt
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@ -153,3 +153,8 @@
0x60 0x6a 0xbb 0xfe
# CHECK: vrintm.f32 s12, s1
0x10 0xa 0xf5 0xee
# CHECK: vmrs r0, mvfr2

6
test/MC/Disassembler/ARM/invalid-because-armv7.txt
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@ -18,3 +18,9 @@
[0x41 0x2b 0xb3 0xbe]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
# Would be vmrs r0, mvfr2
[0x10 0xa 0xf5 0xee]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x10 0xa 0xf5 0xee]