From ef5cd1d3cf7d0b20987a545fcd2d0af2bfe6c422 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Tue, 18 Jan 2005 17:54:55 +0000
Subject: [PATCH] Teach legalize to promote copy(from|to)reg, instead of making
 the isel pass do it.  This results in better code on X86 for floats (because
 if strict precision is not required, we can elide some more expensive double
 -> float conversions like the old isel did), and allows other targets to emit
 CopyFromRegs that are not legal for arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19668 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp      | 17 +++++++++-----
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 22 +------------------
 2 files changed, 13 insertions(+), 26 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 46db8580533..de1cfa21037 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -380,7 +380,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
         Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
       break;
-    case Expand: {
+    case Promote:
+      Tmp2 = PromoteOp(Node->getOperand(1));
+      Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
+      break;
+    case Expand:
       SDOperand Lo, Hi;
       ExpandOp(Node->getOperand(1), Lo, Hi);      
       unsigned Reg = cast<RegSDNode>(Node)->getReg();
@@ -390,10 +394,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
              "Cannot expand multiple times yet (i64 -> i16)");
       break;
     }
-    case Promote:
-      assert(0 && "CopyToReg should not require promotion!");
-      abort();
-    }
     break;
 
   case ISD::RET:
@@ -917,6 +917,13 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
     assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
     break;
+  case ISD::CopyFromReg:
+    Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
+                                Node->getOperand(0));
+    // Remember that we legalized the chain.
+    AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
+    break;
+
   case ISD::SETCC:
     assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
            "SetCC type is not legal??");
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 09b5f3c010b..a17caa1469a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -292,19 +292,7 @@ public:
       FuncInfo.ValueMap.find(V);
     assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
 
-    MVT::ValueType RegVT = VT;
-    if (TLI.getTypeAction(VT) == 1)          // Must promote this value?
-      RegVT = TLI.getTypeToTransformTo(VT);
-
-    N = DAG.getCopyFromReg(VMI->second, RegVT, DAG.getEntryNode());
-
-    if (RegVT != VT)
-      if (MVT::isFloatingPoint(VT))
-        N = DAG.getNode(ISD::FP_ROUND, VT, N);
-      else
-        N = DAG.getNode(ISD::TRUNCATE, VT, N);
-
-    return N;
+    return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
   }
 
   const SDOperand &setValue(const Value *V, SDOperand NewN) {
@@ -843,14 +831,6 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
   assert((Op.getOpcode() != ISD::CopyFromReg ||
           cast<RegSDNode>(Op)->getReg() != Reg) &&
          "Copy from a reg to the same reg!");
-  MVT::ValueType VT = Op.getValueType();
-  if (TLI.getTypeAction(VT) == 1) {       // Must promote this value?
-    if (MVT::isFloatingPoint(VT))
-      Op = DAG.getNode(ISD::FP_EXTEND, TLI.getTypeToTransformTo(VT), Op);
-    else
-      Op = DAG.getNode(ISD::ZERO_EXTEND, TLI.getTypeToTransformTo(VT), Op);
-  }
-
   return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
 }