Added a TLI hook to signal that the target does not have or does not care about

floating point exceptions, added use of flag to fold potentially exception 
raising floating point math in selection DAG. No functionality change, as 
targets have to explicitly ask for this behavior and none does today.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215222 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pedro Artigas 2014-08-08 16:46:53 +00:00
parent 6f3e49e03c
commit ef6ddcf87a
3 changed files with 26 additions and 5 deletions

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@ -261,6 +261,11 @@ public:
bool isMaskAndBranchFoldingLegal() const { bool isMaskAndBranchFoldingLegal() const {
return MaskAndBranchFoldingIsLegal; return MaskAndBranchFoldingIsLegal;
} }
/// Return true if target supports floating point exceptions.
bool hasFloatingPointExceptions() const {
return HasFloatingPointExceptions;
}
/// Return the ValueType of the result of SETCC operations. Also used to /// Return the ValueType of the result of SETCC operations. Also used to
/// obtain the target's preferred type for the condition operand of SELECT and /// obtain the target's preferred type for the condition operand of SELECT and
@ -1063,6 +1068,12 @@ protected:
/// possible, should be replaced by an alternate sequence of instructions not /// possible, should be replaced by an alternate sequence of instructions not
/// containing an integer divide. /// containing an integer divide.
void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
/// Tells the code generator that this target supports floating point
/// exceptions and cares about preserving floating point exception behavior.
void setHasFloatingPointExceptions(bool FPExceptions = true) {
HasFloatingPointExceptions = FPExceptions;
}
/// Tells the code generator which bitwidths to bypass. /// Tells the code generator which bitwidths to bypass.
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
@ -1499,6 +1510,10 @@ private:
/// predication. /// predication.
bool JumpIsExpensive; bool JumpIsExpensive;
/// Whether the target supports or cares about preserving floating point
/// exception behavior.
bool HasFloatingPointExceptions;
/// This target prefers to use _setjmp to implement llvm.setjmp. /// This target prefers to use _setjmp to implement llvm.setjmp.
/// ///
/// Defaults to false. /// Defaults to false.

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@ -3402,6 +3402,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
} }
// Constant fold FP operations. // Constant fold FP operations.
bool HasFPExceptions = TLI->hasFloatingPointExceptions();
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode());
ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode());
if (N1CFP) { if (N1CFP) {
@ -3415,28 +3416,32 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
switch (Opcode) { switch (Opcode) {
case ISD::FADD: case ISD::FADD:
s = V1.add(V2, APFloat::rmNearestTiesToEven); s = V1.add(V2, APFloat::rmNearestTiesToEven);
if (s != APFloat::opInvalidOp) if (!HasFPExceptions || s != APFloat::opInvalidOp)
return getConstantFP(V1, VT); return getConstantFP(V1, VT);
break; break;
case ISD::FSUB: case ISD::FSUB:
s = V1.subtract(V2, APFloat::rmNearestTiesToEven); s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
if (s!=APFloat::opInvalidOp) if (!HasFPExceptions || s!=APFloat::opInvalidOp)
return getConstantFP(V1, VT); return getConstantFP(V1, VT);
break; break;
case ISD::FMUL: case ISD::FMUL:
s = V1.multiply(V2, APFloat::rmNearestTiesToEven); s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
if (s!=APFloat::opInvalidOp) if (!HasFPExceptions || s!=APFloat::opInvalidOp)
return getConstantFP(V1, VT); return getConstantFP(V1, VT);
break; break;
case ISD::FDIV: case ISD::FDIV:
s = V1.divide(V2, APFloat::rmNearestTiesToEven); s = V1.divide(V2, APFloat::rmNearestTiesToEven);
if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) if (!HasFPExceptions || (s!=APFloat::opInvalidOp &&
s!=APFloat::opDivByZero)) {
return getConstantFP(V1, VT); return getConstantFP(V1, VT);
}
break; break;
case ISD::FREM : case ISD::FREM :
s = V1.mod(V2, APFloat::rmNearestTiesToEven); s = V1.mod(V2, APFloat::rmNearestTiesToEven);
if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) if (!HasFPExceptions || (s!=APFloat::opInvalidOp &&
s!=APFloat::opDivByZero)) {
return getConstantFP(V1, VT); return getConstantFP(V1, VT);
}
break; break;
case ISD::FCOPYSIGN: case ISD::FCOPYSIGN:
V1.copySign(V2); V1.copySign(V2);

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@ -705,6 +705,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
JumpIsExpensive = false; JumpIsExpensive = false;
PredictableSelectIsExpensive = false; PredictableSelectIsExpensive = false;
MaskAndBranchFoldingIsLegal = false; MaskAndBranchFoldingIsLegal = false;
HasFloatingPointExceptions = true;
StackPointerRegisterToSaveRestore = 0; StackPointerRegisterToSaveRestore = 0;
ExceptionPointerRegister = 0; ExceptionPointerRegister = 0;
ExceptionSelectorRegister = 0; ExceptionSelectorRegister = 0;