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Add ability to override segment (mostly for code emitter purposes).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2008-10-11 19:09:15 +00:00
parent b7dfaf955b
commit ef93cecd80
4 changed files with 23 additions and 1 deletions
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2
lib/Target/X86/X86.td
View File

@ -116,6 +116,7 @@ def X86InstrInfo : InstrInfo {
"ImmTypeBits",
"FPFormBits",
"hasLockPrefix",
"SegOvrBits",
"Opcode"];
let TSFlagsShifts = [0,
6,
@ -125,6 +126,7 @@ def X86InstrInfo : InstrInfo {
13,
16,
19,
20,
24];
}

10
lib/Target/X86/X86CodeEmitter.cpp
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@ -412,6 +412,16 @@ void Emitter::emitInstruction(const MachineInstr &MI,
// Emit the lock opcode prefix as needed.
if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
// Emit segment overrid opcode prefix as needed.
switch (Desc->TSFlags & X86II::SegOvrMask) {
case X86II::FS:
MCE.emitByte(0x64);
break;
case X86II::GS:
MCE.emitByte(0x65);
break;
}
// Emit the repeat opcode prefix as needed.
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);

3
lib/Target/X86/X86InstrFormats.td
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@ -63,6 +63,8 @@ class OpSize { bit hasOpSizePrefix = 1; }
class AdSize { bit hasAdSizePrefix = 1; }
class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; }
class SegFS { bits<2> SegOvrBits = 1; }
class SegGS { bits<2> SegOvrBits = 2; }
class TB { bits<4> Prefix = 1; }
class REP { bits<4> Prefix = 2; }
class D8 { bits<4> Prefix = 3; }
@ -104,6 +106,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
FPFormat FPForm; // What flavor of FP instruction is this?
bits<3> FPFormBits = 0;
bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
bits<2> SegOvrBits = 0; // Segment override prefix.
}
class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>

9
lib/Target/X86/X86InstrInfo.h
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@ -221,7 +221,14 @@ namespace X86II {
LOCKShift = 19,
LOCK = 1 << LOCKShift,
// Bits 20 -> 23 are unused
// Segment override prefixes. Currently we just need ability to address
// stuff in gs and fs segments.
SegOvrShift = 20,
SegOvrMask = 3 << SegOvrShift,
FS = 1 << SegOvrShift,
GS = 2 << SegOvrShift,
// Bits 22 -> 23 are unused
OpcodeShift = 24,
OpcodeMask = 0xFF << OpcodeShift
};