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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
R600: Add work-around for the CF stack entry HW bug
The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199842 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
39210ac1c6
commit
efa1355495
@ -63,6 +63,11 @@ def FeatureCaymanISA : SubtargetFeature<"caymanISA",
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"true",
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"Use Cayman ISA">;
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def FeatureCFALUBug : SubtargetFeature<"cfalubug",
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"CFALUBug",
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"true",
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"GPU has CF_ALU bug">;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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@ -39,6 +39,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
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EnableIRStructurizer = true;
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EnableIfCvt = true;
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WavefrontSize = 0;
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CFALUBug = false;
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ParseSubtargetFeatures(GPU, FS);
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DevName = GPU;
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}
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@ -97,6 +98,11 @@ AMDGPUSubtarget::getStackEntrySize() const {
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}
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}
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bool
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AMDGPUSubtarget::hasCFAluBug() const {
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assert(getGeneration() <= NORTHERN_ISLANDS);
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return CFALUBug;
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}
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bool
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AMDGPUSubtarget::isTargetELF() const {
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return false;
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}
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@ -52,6 +52,7 @@ private:
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bool EnableIRStructurizer;
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bool EnableIfCvt;
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unsigned WavefrontSize;
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bool CFALUBug;
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InstrItineraryData InstrItins;
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@ -71,6 +72,7 @@ public:
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bool isIfCvtEnabled() const;
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unsigned getWavefrontSize() const;
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unsigned getStackEntrySize() const;
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bool hasCFAluBug() const;
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virtual bool enableMachineScheduler() const {
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return getGeneration() <= NORTHERN_ISLANDS;
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@ -46,13 +46,15 @@ def : Proc<"rv770", R600_VLIW5_Itin,
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//===----------------------------------------------------------------------===//
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def : Proc<"cedar", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32]>;
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[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32,
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FeatureCFALUBug]>;
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def : Proc<"redwood", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
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[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64,
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FeatureCFALUBug]>;
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def : Proc<"sumo", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureWavefrontSize64]>;
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[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]>;
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def : Proc<"juniper", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
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@ -66,13 +68,13 @@ def : Proc<"cypress", R600_VLIW5_Itin,
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//===----------------------------------------------------------------------===//
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def : Proc<"barts", R600_VLIW5_Itin,
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[FeatureNorthernIslands, FeatureVertexCache]>;
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[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
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def : Proc<"turks", R600_VLIW5_Itin,
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[FeatureNorthernIslands, FeatureVertexCache]>;
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[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
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def : Proc<"caicos", R600_VLIW5_Itin,
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[FeatureNorthernIslands]>;
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[FeatureNorthernIslands, FeatureCFALUBug]>;
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def : Proc<"cayman", R600_VLIW4_Itin,
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[FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
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@ -73,6 +73,44 @@ bool CFStack::branchStackContains(CFStack::StackItem Item) {
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return false;
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}
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bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
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if (Opcode == AMDGPU::CF_ALU_PUSH_BEFORE && ST.hasCaymanISA() &&
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getLoopDepth() > 1)
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return true;
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if (!ST.hasCFAluBug())
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return false;
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switch(Opcode) {
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default: return false;
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case AMDGPU::CF_ALU_PUSH_BEFORE:
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case AMDGPU::CF_ALU_ELSE_AFTER:
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case AMDGPU::CF_ALU_BREAK:
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case AMDGPU::CF_ALU_CONTINUE:
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if (CurrentSubEntries == 0)
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return false;
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if (ST.getWavefrontSize() == 64) {
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// We are being conservative here. We only require this work-around if
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// CurrentSubEntries > 3 &&
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// (CurrentSubEntries % 4 == 3 || CurrentSubEntries % 4 == 0)
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//
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// We have to be conservative, because we don't know for certain that
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// our stack allocation algorithm for Evergreen/NI is correct. Applying this
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// work-around when CurrentSubEntries > 3 allows us to over-allocate stack
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// resources without any problems.
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return CurrentSubEntries > 3;
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} else {
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assert(ST.getWavefrontSize() == 32);
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// We are being conservative here. We only require the work-around if
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// CurrentSubEntries > 7 &&
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// (CurrentSubEntries % 8 == 7 || CurrentSubEntries % 8 == 0)
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// See the comment on the wavefront size == 64 case for why we are
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// being conservative.
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return CurrentSubEntries > 7;
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}
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}
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}
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unsigned CFStack::getSubEntrySize(CFStack::StackItem Item) {
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switch(Item) {
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default:
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@ -472,9 +510,12 @@ public:
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if (MI->getOpcode() == AMDGPU::CF_ALU)
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LastAlu.back() = MI;
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I++;
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bool RequiresWorkAround =
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CFStack.requiresWorkAroundForInst(MI->getOpcode());
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switch (MI->getOpcode()) {
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case AMDGPU::CF_ALU_PUSH_BEFORE:
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if (ST.hasCaymanISA() && CFStack.getLoopDepth() > 1) {
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if (RequiresWorkAround) {
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DEBUG(dbgs() << "Applying bug work-around for ALU_PUSH_BEFORE\n");
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::CF_PUSH_EG))
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.addImm(CfCount + 1)
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.addImm(1);
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225
test/CodeGen/R600/cf-stack-bug.ll
Normal file
225
test/CodeGen/R600/cf-stack-bug.ll
Normal file
@ -0,0 +1,225 @@
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; RUN: llc -march=r600 -mcpu=redwood -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=BUG64 --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=sumo -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=BUG64 --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=barts -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=BUG64 --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=turks -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=BUG64 --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=caicos -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=BUG64 --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=cedar -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=BUG32 --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=juniper -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=NOBUG --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=cypress -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=NOBUG --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=cayman -debug-only=r600cf %s -o - 2>&1 | FileCheck %s --check-prefix=NOBUG --check-prefix=FUNC
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; We are currently allocating 2 extra sub-entries on Evergreen / NI for
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; non-WQM push instructions if we change this to 1, then we will need to
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; add one level of depth to each of these tests.
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; BUG64-NOT: Applying bug work-around
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; BUG32-NOT: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: @nested3
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define void @nested3(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.store.1
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if.store.1:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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; BUG64: Applying bug work-around
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; BUG32-NOT: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: @nested4
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define void @nested4(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.1.store
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if.1.store:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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%3 = icmp sgt i32 %cond, 30
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br i1 %3, label %if.4, label %if.3.store
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if.3.store:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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if.4:
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store i32 4, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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; BUG64: Applying bug work-around
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; BUG32-NOT: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: @nested7
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define void @nested7(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.1.store
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if.1.store:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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%3 = icmp sgt i32 %cond, 30
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br i1 %3, label %if.4, label %if.3.store
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if.3.store:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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if.4:
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%4 = icmp sgt i32 %cond, 40
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br i1 %4, label %if.5, label %if.4.store
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if.4.store:
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store i32 4, i32 addrspace(1)* %out
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br label %end
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if.5:
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%5 = icmp sgt i32 %cond, 50
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br i1 %5, label %if.6, label %if.5.store
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if.5.store:
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store i32 5, i32 addrspace(1)* %out
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br label %end
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if.6:
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%6 = icmp sgt i32 %cond, 60
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br i1 %6, label %if.7, label %if.6.store
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if.6.store:
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store i32 6, i32 addrspace(1)* %out
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br label %end
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if.7:
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store i32 7, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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; BUG64: Applying bug work-around
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; BUG32: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: @nested8
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define void @nested8(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.1.store
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if.1.store:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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%3 = icmp sgt i32 %cond, 30
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br i1 %3, label %if.4, label %if.3.store
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if.3.store:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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if.4:
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%4 = icmp sgt i32 %cond, 40
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br i1 %4, label %if.5, label %if.4.store
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if.4.store:
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store i32 4, i32 addrspace(1)* %out
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br label %end
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if.5:
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%5 = icmp sgt i32 %cond, 50
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br i1 %5, label %if.6, label %if.5.store
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if.5.store:
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store i32 5, i32 addrspace(1)* %out
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br label %end
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if.6:
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%6 = icmp sgt i32 %cond, 60
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br i1 %6, label %if.7, label %if.6.store
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if.6.store:
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store i32 6, i32 addrspace(1)* %out
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br label %end
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if.7:
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%7 = icmp sgt i32 %cond, 70
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br i1 %7, label %if.8, label %if.7.store
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if.7.store:
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store i32 7, i32 addrspace(1)* %out
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br label %end
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if.8:
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store i32 8, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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