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Revert "X86: elide comparisons after cmpxchg instructions."
This reverts commit r210523. It was committed prematurely without waiting for review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210524 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
984ee65445
commit
efbf7d1ceb
@ -3504,24 +3504,6 @@ static bool isX86CCUnsigned(unsigned X86CC) {
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llvm_unreachable("covered switch fell through?!");
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}
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/// Convert an integer condition code to an x86 one in the most straightforward
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/// way possible, with no optimisation attempt.
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static unsigned getSimpleX86IntCC(ISD::CondCode SetCCOpcode) {
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switch (SetCCOpcode) {
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default: llvm_unreachable("Invalid integer condition!");
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case ISD::SETEQ: return X86::COND_E;
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case ISD::SETGT: return X86::COND_G;
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case ISD::SETGE: return X86::COND_GE;
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case ISD::SETLT: return X86::COND_L;
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case ISD::SETLE: return X86::COND_LE;
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case ISD::SETNE: return X86::COND_NE;
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case ISD::SETULT: return X86::COND_B;
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case ISD::SETUGT: return X86::COND_A;
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case ISD::SETULE: return X86::COND_BE;
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case ISD::SETUGE: return X86::COND_AE;
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}
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}
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/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
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/// specific condition code, returning the condition code and the LHS/RHS of the
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/// comparison to make.
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@ -3545,7 +3527,19 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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}
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}
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return getSimpleX86IntCC(SetCCOpcode);
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switch (SetCCOpcode) {
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default: llvm_unreachable("Invalid integer condition!");
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case ISD::SETEQ: return X86::COND_E;
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case ISD::SETGT: return X86::COND_G;
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case ISD::SETGE: return X86::COND_GE;
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case ISD::SETLT: return X86::COND_L;
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case ISD::SETLE: return X86::COND_LE;
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case ISD::SETNE: return X86::COND_NE;
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case ISD::SETULT: return X86::COND_B;
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case ISD::SETUGT: return X86::COND_A;
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case ISD::SETULE: return X86::COND_BE;
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case ISD::SETUGE: return X86::COND_AE;
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}
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}
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// First determine if it is required or is profitable to flip the operands.
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@ -10380,77 +10374,10 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
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return SDValue(New.getNode(), 1);
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}
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static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT T = Op.getSimpleValueType();
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SDLoc DL(Op);
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unsigned Reg = 0;
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unsigned size = 0;
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switch(T.SimpleTy) {
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default: llvm_unreachable("Invalid value type!");
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case MVT::i8: Reg = X86::AL; size = 1; break;
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case MVT::i16: Reg = X86::AX; size = 2; break;
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case MVT::i32: Reg = X86::EAX; size = 4; break;
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case MVT::i64:
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assert(Subtarget->is64Bit() && "Node not type legal!");
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Reg = X86::RAX; size = 8;
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break;
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}
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SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
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Op.getOperand(2), SDValue());
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SDValue Ops[] = { cpIn.getValue(0),
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Op.getOperand(1),
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Op.getOperand(3),
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DAG.getTargetConstant(size, MVT::i8),
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cpIn.getValue(1) };
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
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SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
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Ops, T, MMO);
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SDValue cpOut =
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DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
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return cpOut;
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}
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something equivalent
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/// and set X86CC to the needed condition code to make use of the
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/// comparison. This may not be the obvious equivalent to CC if the comparison
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/// can be achieved more efficiently using a different method.
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SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, ISD::CondCode CC,
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SDLoc dl, SelectionDAG &DAG,
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unsigned &X86CC) const {
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// A cmpxchg instruction will actually perform the comparison
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if ((Op0.getOpcode() == ISD::ATOMIC_CMP_SWAP && Op0.getOperand(2) == Op1) ||
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(Op1.getOpcode() == ISD::ATOMIC_CMP_SWAP && Op1.getOperand(2) == Op0)) {
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SDValue CmpSwap;
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if (Op0.getOpcode() == ISD::ATOMIC_CMP_SWAP) {
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// x86's cmpxchg instruction performs the equivalent of "cmp desired,
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// loaded".
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CmpSwap = Op0;
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CC = getSetCCSwappedOperands(CC);
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} else
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CmpSwap = Op1;
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// Lowering the CmpSwap node gives us a getCopyFromReg SDValue representing
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// the value loaded. I.e. the ATOMIC_CMP_SWAP
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X86CC = getSimpleX86IntCC(CC);
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SDValue EFLAGS = LowerCMP_SWAP(CmpSwap, Subtarget, DAG);
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DAG.ReplaceAllUsesOfValueWith(CmpSwap.getValue(0), EFLAGS);
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// Glue on a copy from EFLAGS to be used in place of the required Cmp.
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EFLAGS = DAG.getCopyFromReg(EFLAGS.getValue(1), dl, X86::EFLAGS,
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MVT::i32, EFLAGS.getValue(2));
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DAG.ReplaceAllUsesOfValueWith(CmpSwap.getValue(1), EFLAGS.getValue(1));
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return EFLAGS;
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}
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bool IsFP = Op1.getSimpleValueType().isFloatingPoint();
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X86CC = TranslateX86CC(CC, IsFP, Op0, Op1, DAG);
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if (X86CC == X86::COND_INVALID)
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return SDValue();
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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/// equivalent.
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SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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SDLoc dl, SelectionDAG &DAG) const {
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
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if (C->getAPIntValue() == 0)
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return EmitTest(Op0, X86CC, dl, DAG);
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@ -10458,7 +10385,7 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, ISD::CondCode CC,
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if (Op0.getValueType() == MVT::i1)
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llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
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}
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if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
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Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
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// Do the comparison at i32 if it's smaller, besides the Atom case.
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@ -11024,11 +10951,12 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
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}
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unsigned X86CC;
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SDValue EFLAGS = EmitCmp(Op0, Op1, CC, dl, DAG, X86CC);
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if (!EFLAGS.getNode())
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bool isFP = Op1.getSimpleValueType().isFloatingPoint();
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unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
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if (X86CC == X86::COND_INVALID)
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return SDValue();
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SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
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EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
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SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), EFLAGS);
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@ -11456,14 +11384,6 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
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Cond = Cmp;
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addTest = false;
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} else if (Opc == ISD::CopyFromReg &&
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Cmp->getOperand(0)->getOpcode() == ISD::CopyFromReg &&
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Cmp->getOperand(0)->getOperand(0)->getOpcode() ==
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X86ISD::LCMPXCHG_DAG) {
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assert(cast<RegisterSDNode>(Cmp->getOperand(1))->getReg() == X86::EFLAGS);
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Chain = Cmp.getValue(1);
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Cond = Cmp;
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addTest = false;
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} else {
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switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
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default: break;
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@ -14443,6 +14363,38 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
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return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
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}
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static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT T = Op.getSimpleValueType();
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SDLoc DL(Op);
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unsigned Reg = 0;
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unsigned size = 0;
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switch(T.SimpleTy) {
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default: llvm_unreachable("Invalid value type!");
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case MVT::i8: Reg = X86::AL; size = 1; break;
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case MVT::i16: Reg = X86::AX; size = 2; break;
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case MVT::i32: Reg = X86::EAX; size = 4; break;
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case MVT::i64:
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assert(Subtarget->is64Bit() && "Node not type legal!");
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Reg = X86::RAX; size = 8;
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break;
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}
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SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
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Op.getOperand(2), SDValue());
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SDValue Ops[] = { cpIn.getValue(0),
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Op.getOperand(1),
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Op.getOperand(3),
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DAG.getTargetConstant(size, MVT::i8),
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cpIn.getValue(1) };
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
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SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
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Ops, T, MMO);
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SDValue cpOut =
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DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
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return cpOut;
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}
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static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT SrcVT = Op.getOperand(0).getSimpleValueType();
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@ -1006,10 +1006,9 @@ namespace llvm {
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SelectionDAG &DAG) const;
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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/// equivalent, possibly adjusting the condition code to a more appropriate
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/// x86 form.
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SDValue EmitCmp(SDValue Op0, SDValue Op1, ISD::CondCode CC, SDLoc dl,
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SelectionDAG &DAG, unsigned &X86CC) const;
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
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SelectionDAG &DAG) const;
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/// Convert a comparison if required by the subtarget.
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SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
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@ -1,82 +0,0 @@
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; RUN: llc -mtriple=x86_64 -o - %s | FileCheck %s
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define i1 @try_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: try_cmpxchg:
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; CHECK: cmpxchgl
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; CHECK-NOT: cmp
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; CHECK: sete %al
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; CHECK: retq
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%old = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = icmp eq i32 %old, %desired
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ret i1 %success
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}
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define void @cmpxchg_flow(i64* %addr, i64 %desired, i64 %new) {
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; CHECK-LABEL: cmpxchg_flow:
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; CHECK: cmpxchgq
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; CHECK-NOT: cmp
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; CHECK-NOT: set
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; CHECK: {{jne|jeq}}
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%old = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst seq_cst
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%success = icmp eq i64 %old, %desired
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br i1 %success, label %true, label %false
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true:
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call void @foo()
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ret void
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false:
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call void @bar()
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ret void
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}
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define i1 @cmpxchg_arithcmp(i16* %addr, i16 %desired, i16 %new) {
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; CHECK-LABEL: cmpxchg_arithcmp:
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; CHECK: cmpxchgw
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; CHECK-NOT: cmp
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; CHECK: setbe %al
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; CHECK: retq
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%old = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst seq_cst
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%success = icmp uge i16 %old, %desired
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ret i1 %success
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}
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define i1 @cmpxchg_arithcmp_swapped(i8* %addr, i8 %desired, i8 %new) {
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; CHECK-LABEL: cmpxchg_arithcmp_swapped:
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; CHECK: cmpxchgb
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; CHECK-NOT: cmp
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; CHECK: setge %al
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; CHECK: retq
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%old = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst seq_cst
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%success = icmp sge i8 %desired, %old
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ret i1 %success
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}
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define i64 @cmpxchg_sext(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: cmpxchg_sext:
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; CHECK-DAG: cmpxchgl
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; CHECK-DAG: movq $-1, %rax
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; CHECK-DAG: xorl %e[[ZERO:[a-z0-9]+]], %e[[ZERO]]
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; CHECK-NOT: cmpl
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; CHECK: cmovneq %r[[ZERO]], %rax
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; CHECK: retq
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%old = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = icmp eq i32 %old, %desired
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%mask = sext i1 %success to i64
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ret i64 %mask
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}
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define i32 @cmpxchg_zext(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: cmpxchg_zext:
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; CHECK: cmpxchgl
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; CHECK-NOT: cmp
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; CHECK: sete [[BYTE:%[a-z0-9]+]]
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; CHECK: movzbl [[BYTE]], %eax
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%old = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = icmp eq i32 %old, %desired
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%mask = zext i1 %success to i32
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ret i32 %mask
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}
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declare void @foo()
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declare void @bar()
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