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Reject really weird coalescer case when trying to merge identical subregisters

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of different register classes. e.g.

  %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3

Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.

This should unbreak the dragonegg builder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102672 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-04-29 23:47:46 +00:00
parent 8d0e1bcc92
commit f07fc974d3
2 changed files with 149 additions and 0 deletions
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7
lib/CodeGen/SimpleRegisterCoalescing.cpp
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@ -1394,6 +1394,13 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
return false; // Not coalescable.
}
// We cannot handle dual subreg indices and mismatched classes at the same
// time.
if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
return false;
}
// Check that a physical source register is compatible with dst regclass
if (SrcIsPhys) {
unsigned SrcSubReg = SrcSubIdx ?