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- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.

Browse Source 
- Fix some copy+paste bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-10-18 22:40:57 +00:00
parent 58184e6878
commit f0a0cddbcd
15 changed files with 58 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
include/llvm/Target/MRegisterInfo.h
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@@ -508,7 +508,7 @@ public:
const TargetRegisterClass *RC) const = 0; const TargetRegisterClass *RC) const = 0;
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const = 0; SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
@@ -518,7 +518,7 @@ public:
const TargetRegisterClass *RC) const = 0; const TargetRegisterClass *RC) const = 0;
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const =0; SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
@@ -577,6 +577,14 @@ public:
return false; return false;
} }
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
/// instruction after load / store are unfolded from the specified opcode.
/// It returns zero if the specified unfolding is impossible.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore) const {
return 0;
}
/// targetHandlesStackFrameRounding - Returns true if the target is /// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue /// responsible for rounding up the stack frame (probably at emitPrologue
/// time). /// time).

4
lib/Target/ARM/ARMRegisterInfo.cpp
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@@ -183,7 +183,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} }
void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;
@@ -239,7 +239,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} }
void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;

4
lib/Target/ARM/ARMRegisterInfo.h
View File

@@ -52,7 +52,7 @@ public:
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -62,7 +62,7 @@ public:
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;

4
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@@ -83,7 +83,7 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} }
void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;
@@ -128,7 +128,7 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} }
void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;

4
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@@ -34,7 +34,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -44,7 +44,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;

4
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@@ -61,7 +61,7 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} }
void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;
@@ -113,7 +113,7 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} }
void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;

4
lib/Target/IA64/IA64RegisterInfo.h
View File

@@ -35,7 +35,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -45,7 +45,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;

4
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@@ -96,7 +96,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} }
void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (RC != Mips::CPURegsRegisterClass) if (RC != Mips::CPURegsRegisterClass)
@@ -128,7 +128,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} }
void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (RC != Mips::CPURegsRegisterClass) if (RC != Mips::CPURegsRegisterClass)

4
lib/Target/Mips/MipsRegisterInfo.h
View File

@@ -38,7 +38,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -48,7 +48,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;

4
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@@ -182,7 +182,7 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} }
void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (Addr[0].isFrameIndex()) { if (Addr[0].isFrameIndex()) {
@@ -291,7 +291,7 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} }
void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (Addr[0].isFrameIndex()) { if (Addr[0].isFrameIndex()) {

4
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@@ -41,7 +41,7 @@ public:
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -51,7 +51,7 @@ public:
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;

4
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@@ -49,7 +49,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} }
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;
@@ -91,7 +91,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
} }
void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0; unsigned Opc = 0;

4
lib/Target/Sparc/SparcRegisterInfo.h
View File

@@ -36,7 +36,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -46,7 +46,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;

18
lib/Target/X86/X86RegisterInfo.cpp
View File

@@ -806,7 +806,7 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} }
void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = getStoreRegOpcode(RC); unsigned Opc = getStoreRegOpcode(RC);
@@ -862,7 +862,7 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} }
void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const { SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = getLoadRegOpcode(RC); unsigned Opc = getLoadRegOpcode(RC);
@@ -1273,6 +1273,20 @@ X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
return true; return true;
} }
unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore) const {
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
MemOp2RegOpTable.find((unsigned*)Opc);
if (I == MemOp2RegOpTable.end())
return 0;
bool HasLoad = I->second.second & (1 << 4);
bool HasStore = I->second.second & (1 << 5);
if (UnfoldLoad && !HasLoad)
return 0;
if (UnfoldStore && !HasStore)
return 0;
return I->second.first;
}
const unsigned * const unsigned *
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

10
lib/Target/X86/X86RegisterInfo.h
View File

@@ -89,7 +89,7 @@ public:
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -99,7 +99,7 @@ public:
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -142,6 +142,12 @@ public:
bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
SmallVectorImpl<SDNode*> &NewNodes) const; SmallVectorImpl<SDNode*> &NewNodes) const;
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
/// instruction after load / store are unfolded from the specified opcode.
/// It returns zero if the specified unfolding is impossible.
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore) const;
/// getCalleeSavedRegs - Return a null-terminated list of all of the /// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target. /// callee-save registers on this target.
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;