mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-10 02:36:06 +00:00
Shrink down SSE3 code by more multiclass refactoring
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
cf22493496
commit
f12ad66741
@ -3350,15 +3350,9 @@ let Constraints = "$src1 = $dst" in {
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}
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//===---------------------------------------------------------------------===//
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// SSSE3 Instructions
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// SSSE3 - Packed Absolute Instructions
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//===---------------------------------------------------------------------===//
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// Thread synchronization
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def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
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[(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
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def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
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[(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
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/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, PatFrag mem_frag128,
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@ -3396,149 +3390,100 @@ defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
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int_x86_ssse3_pabs_d,
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int_x86_ssse3_pabs_d_128>;
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/// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
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let Constraints = "$src1 = $dst" in {
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multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Binary Operator Instructions
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//===---------------------------------------------------------------------===//
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, PatFrag mem_frag128,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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let isCommutable = 1 in
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize;
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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/// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
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let Constraints = "$src1 = $dst" in {
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multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv4i16 addr:$src2))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
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}
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// None of these have i8 immediate fields.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_w,
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int_x86_ssse3_phadd_w_128>;
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defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
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int_x86_ssse3_phadd_d,
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int_x86_ssse3_phadd_d_128>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_sw,
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int_x86_ssse3_phadd_sw_128>;
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defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_w,
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int_x86_ssse3_phsub_w_128>;
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defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
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int_x86_ssse3_phsub_d,
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int_x86_ssse3_phsub_d_128>;
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_sw,
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
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int_x86_ssse3_pmadd_ub_sw,
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int_x86_ssse3_pmadd_ub_sw_128>;
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
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int_x86_ssse3_pshuf_b,
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int_x86_ssse3_pshuf_b_128>;
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
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int_x86_ssse3_psign_b,
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int_x86_ssse3_psign_b_128>;
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defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
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int_x86_ssse3_psign_w,
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int_x86_ssse3_psign_w_128>;
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
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int_x86_ssse3_psign_d,
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int_x86_ssse3_psign_d_128>;
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}
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defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
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int_x86_ssse3_pmul_hr_sw,
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int_x86_ssse3_pmul_hr_sw_128>;
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}
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/// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
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let Constraints = "$src1 = $dst" in {
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multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv2i32 addr:$src2))))]>;
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
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}
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}
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Align Instruction Patterns
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//===---------------------------------------------------------------------===//
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let ImmT = NoImm in { // None of these have i8 immediate fields.
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defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
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int_x86_ssse3_phadd_w,
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int_x86_ssse3_phadd_w_128>;
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defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
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int_x86_ssse3_phadd_d,
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int_x86_ssse3_phadd_d_128>;
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defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
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int_x86_ssse3_phadd_sw,
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int_x86_ssse3_phadd_sw_128>;
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defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
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int_x86_ssse3_phsub_w,
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int_x86_ssse3_phsub_w_128>;
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defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
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int_x86_ssse3_phsub_d,
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int_x86_ssse3_phsub_d_128>;
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defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
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int_x86_ssse3_phsub_sw,
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw,
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int_x86_ssse3_pmadd_ub_sw_128>;
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defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw,
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int_x86_ssse3_pmul_hr_sw_128, 1>;
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defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
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int_x86_ssse3_pshuf_b,
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int_x86_ssse3_pshuf_b_128>;
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defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
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int_x86_ssse3_psign_b,
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int_x86_ssse3_psign_b_128>;
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defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
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int_x86_ssse3_psign_w,
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int_x86_ssse3_psign_w_128>;
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defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
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int_x86_ssse3_psign_d,
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int_x86_ssse3_psign_d_128>;
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}
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// palignr patterns.
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let Constraints = "$src1 = $dst" in {
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def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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@ -3600,10 +3545,15 @@ def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
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Requires<[HasSSSE3]>;
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}
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
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//===---------------------------------------------------------------------===//
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// SSSE3 Misc Instructions
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//===---------------------------------------------------------------------===//
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// Thread synchronization
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def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
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[(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
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def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
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[(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
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//===---------------------------------------------------------------------===//
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// Non-Instruction Patterns
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