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Don't model the fetch and decode units for the PPC440

Browse Source 
Modeling the fetch and decode units in the PPC440 itinerary does not add
anything to the hazard detection capability (and so modeling them just wastes
compile time).

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195946 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-11-29 05:58:38 +00:00
parent 3d9cfe7e99
commit f13a4e6e7b
1 changed files with 61 additions and 180 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

241
lib/Target/PowerPC/PPCSchedule440.td
View File

@ -26,10 +26,6 @@
//===----------------------------------------------------------------------===//
// Functional units on the PowerPC 440/450 chip sets
//
def P440_IFTH1 : FuncUnit; // Fetch unit 1
def P440_IFTH2 : FuncUnit; // Fetch unit 2
def P440_PDCD1 : FuncUnit; // Decode unit 1
def P440_PDCD2 : FuncUnit; // Decode unit 2
def P440_DISS1 : FuncUnit; // Issue unit 1
def P440_DISS2 : FuncUnit; // Issue unit 2
def P440_LRACC : FuncUnit; // Register access and dispatch for
@ -104,15 +100,12 @@ def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
def PPC440Itineraries : ProcessorItineraries<
[P440_IFTH1, P440_IFTH2, P440_PDCD1, P440_PDCD2, P440_DISS1, P440_DISS2,
P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2, P440_IWB, P440_LRACC,
P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD, P440_LWB, P440_FEXE1,
P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5, P440_FEXE6, P440_FWB,
P440_LWARX_Hold],
[P440_DISS1, P440_DISS2, P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2,
P440_IWB, P440_LRACC, P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD,
P440_LWB, P440_FEXE1, P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5,
P440_FEXE6, P440_FWB, P440_LWARX_Hold],
[P440_GPR_Bypass, P440_FPR_Bypass], [
InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC, P440_LRACC]>,
InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
@ -120,9 +113,7 @@ def PPC440Itineraries : ProcessorItineraries<
[6, 4, 4],
[P440_GPR_Bypass,
P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC, P440_LRACC]>,
InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
@ -130,27 +121,21 @@ def PPC440Itineraries : ProcessorItineraries<
[6, 4, 4],
[P440_GPR_Bypass,
P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC, P440_LRACC]>,
InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
InstrStage<1, [P440_IWB, P440_JWB]>],
[6, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<33, [P440_IWB]>],
[40, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
@ -158,9 +143,7 @@ def PPC440Itineraries : ProcessorItineraries<
[7, 4, 4],
[P440_GPR_Bypass,
P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
@ -168,36 +151,28 @@ def PPC440Itineraries : ProcessorItineraries<
[7, 4, 4],
[P440_GPR_Bypass,
P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC, P440_LRACC]>,
InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
@ -205,9 +180,7 @@ def PPC440Itineraries : ProcessorItineraries<
[6, 4, 4],
[P440_GPR_Bypass,
P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC, P440_LRACC]>,
InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
@ -215,189 +188,147 @@ def PPC440Itineraries : ProcessorItineraries<
[6, 4, 4],
[P440_GPR_Bypass,
P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[6, 4],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_BrB, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_BrB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4, 4],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[9, 5],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[9, 5],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5, 5],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5, 5],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[9, 5, 5],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[9, 5, 5],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
InstrStage<4, [P440_LWARX_Hold], 0>,
InstrStage<1, [P440_LRACC]>,
@ -406,27 +337,21 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
InstrStage<4, [P440_LWARX_Hold], 0>,
InstrStage<1, [P440_LRACC]>,
@ -435,9 +360,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
InstrStage<4, [P440_LWARX_Hold], 0>,
InstrStage<1, [P440_LRACC]>,
@ -446,16 +369,12 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [P440_LWB]>],
[8, 5],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<3, [P440_AGEN], 1>,
InstrStage<2, [P440_CRD], 1>,
InstrStage<1, [P440_LWB]>]>,
InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC], 0>,
InstrStage<1, [P440_LRACC], 0>,
InstrStage<1, [P440_IRACC]>,
@ -471,115 +390,89 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<6, [P440_LWB], 0>,
InstrStage<6, [P440_JWB], 0>,
InstrStage<6, [P440_IWB]>]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[6, 4],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[6, 4],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<3, [P440_IWB]>],
[9, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[7, 4],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<3, [P440_IWB]>],
[10, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<3, [P440_IWB]>],
[10, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<3, [P440_IWB]>],
[10, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<3, [P440_IWB]>],
[10, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_SprSC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_SprSC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_IRACC]>,
InstrStage<1, [P440_IEXE1]>,
InstrStage<1, [P440_IEXE2]>,
InstrStage<1, [P440_IWB]>],
[8, 4],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,
@ -591,9 +484,7 @@ def PPC440Itineraries : ProcessorItineraries<
[10, 4, 4],
[P440_FPR_Bypass,
P440_FPR_Bypass, P440_FPR_Bypass]>,
InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,
@ -605,9 +496,7 @@ def PPC440Itineraries : ProcessorItineraries<
[10, 4, 4],
[P440_FPR_Bypass,
P440_FPR_Bypass, P440_FPR_Bypass]>,
InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,
@ -619,9 +508,7 @@ def PPC440Itineraries : ProcessorItineraries<
[10, 4, 4],
[P440_FPR_Bypass, P440_FPR_Bypass,
P440_FPR_Bypass]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,
@ -632,9 +519,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<25, [P440_FWB]>],
[35, 4, 4],
[NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,
@ -645,9 +530,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<13, [P440_FWB]>],
[23, 4, 4],
[NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
InstrItinData<IIC_FPFused, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPFused, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,
@ -660,9 +543,7 @@ def PPC440Itineraries : ProcessorItineraries<
[P440_FPR_Bypass,
P440_FPR_Bypass, P440_FPR_Bypass,
P440_FPR_Bypass]>,
InstrItinData<IIC_FPRes, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrItinData<IIC_FPRes, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_FRACC]>,
InstrStage<1, [P440_FEXE1]>,
InstrStage<1, [P440_FEXE2]>,