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Switch some getAliasSet clients to MCRegAliasIterator.

Browse Source 
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157837 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-06-01 20:36:54 +00:00
parent 73c2f7f5ed
commit f152fe8d48
8 changed files with 46 additions and 99 deletions
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15
lib/CodeGen/BranchFolding.cpp
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@ -1491,9 +1491,8 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
if (!Reg) if (!Reg)
continue; continue;
if (MO.isUse()) { if (MO.isUse()) {
Uses.insert(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) Uses.insert(*AI);
Uses.insert(*AS);
} else if (!MO.isDead()) } else if (!MO.isDead())
// Don't try to hoist code in the rare case the terminator defines a // Don't try to hoist code in the rare case the terminator defines a
// register that is later used. // register that is later used.
@ -1553,18 +1552,16 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
if (!Reg) if (!Reg)
continue; continue;
if (MO.isUse()) { if (MO.isUse()) {
Uses.insert(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) Uses.insert(*AI);
Uses.insert(*AS);
} else { } else {
if (Uses.count(Reg)) { if (Uses.count(Reg)) {
Uses.erase(Reg); Uses.erase(Reg);
for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
Uses.erase(*SR); // Use getSubRegisters to be conservative Uses.erase(*SR); // Use getSubRegisters to be conservative
} }
Defs.insert(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) Defs.insert(*AI);
Defs.insert(*AS);
} }
} }

50
lib/CodeGen/CriticalAntiDepBreaker.cpp
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@ -62,17 +62,11 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
// In a return block, examine the function live-out regs. // In a return block, examine the function live-out regs.
for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(), for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
E = MRI.liveout_end(); I != E; ++I) { E = MRI.liveout_end(); I != E; ++I) {
unsigned Reg = *I; for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); unsigned Reg = *AI;
KillIndices[Reg] = BBSize; Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
DefIndices[Reg] = ~0u; KillIndices[Reg] = BBSize;
DefIndices[Reg] = ~0u;
// Repeat, for all aliases.
for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[AliasReg] = BBSize;
DefIndices[AliasReg] = ~0u;
} }
} }
} }
@ -84,17 +78,11 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
SE = BB->succ_end(); SI != SE; ++SI) SE = BB->succ_end(); SI != SE; ++SI)
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) { E = (*SI)->livein_end(); I != E; ++I) {
unsigned Reg = *I; for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); unsigned Reg = *AI;
KillIndices[Reg] = BBSize; Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
DefIndices[Reg] = ~0u; KillIndices[Reg] = BBSize;
DefIndices[Reg] = ~0u;
// Repeat, for all aliases.
for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[AliasReg] = BBSize;
DefIndices[AliasReg] = ~0u;
} }
} }
@ -104,18 +92,12 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
const MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineFrameInfo *MFI = MF.getFrameInfo();
BitVector Pristine = MFI->getPristineRegs(BB); BitVector Pristine = MFI->getPristineRegs(BB);
for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
unsigned Reg = *I; if (!IsReturnBlock && !Pristine.test(*I)) continue;
if (!IsReturnBlock && !Pristine.test(Reg)) continue; for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); unsigned Reg = *AI;
KillIndices[Reg] = BBSize; Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
DefIndices[Reg] = ~0u; KillIndices[Reg] = BBSize;
DefIndices[Reg] = ~0u;
// Repeat, for all aliases.
for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[AliasReg] = BBSize;
DefIndices[AliasReg] = ~0u;
} }
} }
} }

6
lib/CodeGen/DeadMachineInstructionElim.cpp
View File

@ -187,10 +187,8 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
if (MO.isReg() && MO.isUse()) { if (MO.isReg() && MO.isUse()) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg)) { if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
LivePhysRegs.set(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
for (const uint16_t *AliasSet = TRI->getAliasSet(Reg); LivePhysRegs.set(*AI);
*AliasSet; ++AliasSet)
LivePhysRegs.set(*AliasSet);
} }
} }
} }

5
lib/CodeGen/MachineCSE.cpp
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@ -216,11 +216,10 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
if (MO.isDef() && if (MO.isDef() &&
(MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end()))) (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
continue; continue;
PhysRefs.insert(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
PhysRefs.insert(*AI);
if (MO.isDef()) if (MO.isDef())
PhysDefs.push_back(Reg); PhysDefs.push_back(Reg);
for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
PhysRefs.insert(*Alias);
} }
return !PhysRefs.empty(); return !PhysRefs.empty();

40
lib/CodeGen/MachineCopyPropagation.cpp
View File

@ -62,26 +62,14 @@ void
MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg, MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg,
SourceMap &SrcMap, SourceMap &SrcMap,
DenseMap<unsigned, MachineInstr*> &AvailCopyMap) { DenseMap<unsigned, MachineInstr*> &AvailCopyMap) {
SourceMap::iterator SI = SrcMap.find(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
if (SI != SrcMap.end()) { SourceMap::iterator SI = SrcMap.find(*AI);
const DestList& Defs = SI->second;
for (DestList::const_iterator I = Defs.begin(), E = Defs.end();
I != E; ++I) {
unsigned MappedDef = *I;
// Source of copy is no longer available for propagation.
if (AvailCopyMap.erase(MappedDef)) {
for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR)
AvailCopyMap.erase(*SR);
}
}
}
for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
SI = SrcMap.find(*AS);
if (SI != SrcMap.end()) { if (SI != SrcMap.end()) {
const DestList& Defs = SI->second; const DestList& Defs = SI->second;
for (DestList::const_iterator I = Defs.begin(), E = Defs.end(); for (DestList::const_iterator I = Defs.begin(), E = Defs.end();
I != E; ++I) { I != E; ++I) {
unsigned MappedDef = *I; unsigned MappedDef = *I;
// Source of copy is no longer available for propagation.
if (AvailCopyMap.erase(MappedDef)) { if (AvailCopyMap.erase(MappedDef)) {
for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR)
AvailCopyMap.erase(*SR); AvailCopyMap.erase(*SR);
@ -188,11 +176,8 @@ bool MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
} }
// If Src is defined by a previous copy, it cannot be eliminated. // If Src is defined by a previous copy, it cannot be eliminated.
CI = CopyMap.find(Src); for (MCRegAliasIterator AI(Src, TRI, true); AI.isValid(); ++AI) {
if (CI != CopyMap.end()) CI = CopyMap.find(*AI);
MaybeDeadCopies.remove(CI->second);
for (const uint16_t *AS = TRI->getAliasSet(Src); *AS; ++AS) {
CI = CopyMap.find(*AS);
if (CI != CopyMap.end()) if (CI != CopyMap.end())
MaybeDeadCopies.remove(CI->second); MaybeDeadCopies.remove(CI->second);
} }
@ -256,11 +241,8 @@ bool MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
// If 'Reg' is defined by a copy, the copy is no longer a candidate // If 'Reg' is defined by a copy, the copy is no longer a candidate
// for elimination. // for elimination.
DenseMap<unsigned, MachineInstr*>::iterator CI = CopyMap.find(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
if (CI != CopyMap.end()) DenseMap<unsigned, MachineInstr*>::iterator CI = CopyMap.find(*AI);
MaybeDeadCopies.remove(CI->second);
for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
CI = CopyMap.find(*AS);
if (CI != CopyMap.end()) if (CI != CopyMap.end())
MaybeDeadCopies.remove(CI->second); MaybeDeadCopies.remove(CI->second);
} }
@ -296,11 +278,9 @@ bool MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
unsigned Reg = Defs[i]; unsigned Reg = Defs[i];
// No longer defined by a copy. // No longer defined by a copy.
CopyMap.erase(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
AvailCopyMap.erase(Reg); CopyMap.erase(*AI);
for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) { AvailCopyMap.erase(*AI);
CopyMap.erase(*AS);
AvailCopyMap.erase(*AS);
} }
// If 'Reg' is previously source of a copy, it is no longer available for // If 'Reg' is previously source of a copy, it is no longer available for

7
lib/Target/Hexagon/HexagonCallingConvLower.cpp
View File

@ -56,11 +56,8 @@ void Hexagon_CCState::HandleByVal(unsigned ValNo, EVT ValVT,
/// MarkAllocated - Mark a register and all of its aliases as allocated. /// MarkAllocated - Mark a register and all of its aliases as allocated.
void Hexagon_CCState::MarkAllocated(unsigned Reg) { void Hexagon_CCState::MarkAllocated(unsigned Reg) {
UsedRegs[Reg/32] |= 1 << (Reg&31); for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
UsedRegs[*AI/32] |= 1 << (*AI&31);
if (const uint16_t *RegAliases = TRI.getAliasSet(Reg))
for (; (Reg = *RegAliases); ++RegAliases)
UsedRegs[Reg/32] |= 1 << (Reg&31);
} }
/// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node, /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,

11
lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -251,13 +251,10 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
//returns true if the Reg or its alias is in the RegSet. //returns true if the Reg or its alias is in the RegSet.
bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) { bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) {
if (RegSet.count(Reg)) // Check Reg and all aliased Registers.
return true; for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
// check Aliased Registers AI.isValid(); ++AI)
for (const uint16_t *Alias = TM.getRegisterInfo()->getAliasSet(Reg); if (RegSet.count(*AI))
*Alias; ++Alias)
if (RegSet.count(*Alias))
return true; return true;
return false; return false;
} }

11
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -279,14 +279,11 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
//returns true if the Reg or its alias is in the RegSet. //returns true if the Reg or its alias is in the RegSet.
bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
{ {
if (RegSet.count(Reg)) // Check Reg and all aliased Registers.
return true; for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
// check Aliased Registers AI.isValid(); ++AI)
for (const uint16_t *Alias = TM.getRegisterInfo()->getAliasSet(Reg); if (RegSet.count(*AI))
*Alias; ++ Alias)
if (RegSet.count(*Alias))
return true; return true;
return false; return false;
} }