mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 06:33:24 +00:00
ARM: improve RTABI 4.2 conformance on Linux
The set of functions defined in the RTABI was separated for no real reason. This brings us closer to proper utilisation of the functions defined by the RTABI. It also sets the ground for correctly emitting function calls to AEABI functions on all AEABI conforming platforms. The previously existing lie on the behaviour of __ldivmod and __uldivmod is propagated as it is beyond the scope of the change. The changes to the test are due to the fact that we now use the divmod functions which return both the quotient and remainder and thus we no longer need to invoke two functions on Linux (making it closer to EABI's behaviour). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool
parent
c5b413060c
commit
f15492fd72
@ -312,8 +312,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
// Conversions between floating types.
|
||||
// RTABI chapter 4.1.2, Table 7
|
||||
{ RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
|
||||
// Integer to floating-point conversions.
|
||||
// RTABI chapter 4.1.2, Table 8
|
||||
@ -328,21 +328,31 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
|
||||
// Long long helper functions
|
||||
// RTABI chapter 4.2, Table 9
|
||||
{ RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
// FIXME: __aeabi_ldivmod is SDIVREM not SDIV; we should custom lower this
|
||||
{ RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
// FIXME: __aeabi_uldivmod is UDIVREM not UDIV; we should custom lower this
|
||||
{ RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
|
||||
// Integer division functions
|
||||
// RTABI chapter 4.3.1
|
||||
{ RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
{ RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
|
||||
|
||||
// Memory operations
|
||||
// RTABI chapter 4.3.4
|
||||
@ -357,6 +367,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
if (LC.Cond != ISD::SETCC_INVALID)
|
||||
setCmpLibcallCC(LC.Op, LC.Cond);
|
||||
}
|
||||
|
||||
setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
|
||||
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
|
||||
}
|
||||
|
||||
if (Subtarget->isTargetWindows()) {
|
||||
@ -676,31 +689,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
}
|
||||
|
||||
// FIXME: Also set divmod for SREM on EABI
|
||||
setOperationAction(ISD::SREM, MVT::i32, Expand);
|
||||
setOperationAction(ISD::UREM, MVT::i32, Expand);
|
||||
// Register based DivRem for AEABI (RTABI 4.2)
|
||||
if (Subtarget->isTargetAEABI()) {
|
||||
setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
|
||||
setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
|
||||
setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
|
||||
setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
|
||||
setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
|
||||
setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
|
||||
setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
|
||||
setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
|
||||
|
||||
setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
|
||||
setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
|
||||
|
||||
setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
|
||||
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
|
||||
} else {
|
||||
setOperationAction(ISD::SREM, MVT::i32, Expand);
|
||||
setOperationAction(ISD::UREM, MVT::i32, Expand);
|
||||
if (!Subtarget->isTargetAEABI()) {
|
||||
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
|
||||
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
|
||||
}
|
||||
|
||||
@ -17,10 +17,7 @@ entry:
|
||||
; EABI: __aeabi_idivmod
|
||||
; EABI: mov [[div:r[0-9]+]], r0
|
||||
; EABI: mov [[rem:r[0-9]+]], r1
|
||||
; GNU: __aeabi_idiv
|
||||
; GNU: mov [[sum:r[0-9]+]], r0
|
||||
; GNU: __modsi3
|
||||
; GNU: add [[sum]]{{.*}}r0
|
||||
; GNU: __aeabi_idivmod
|
||||
; DARWIN: ___divsi3
|
||||
; DARWIN: mov [[sum:r[0-9]+]], r0
|
||||
; DARWIN: __modsi3
|
||||
@ -34,7 +31,7 @@ entry:
|
||||
%conv14 = trunc i32 %add13 to i16
|
||||
; EABI: add r0{{.*}}r1
|
||||
; EABI: sxth r0, r0
|
||||
; GNU: add r0{{.*}}[[sum]]
|
||||
; GNU: add r0{{.*}}
|
||||
; GNU: sxth r0, r0
|
||||
; DARWIN: add r0{{.*}}[[sum]]
|
||||
; DARWIN: sxth r0, r0
|
||||
@ -51,10 +48,7 @@ entry:
|
||||
; EABI: __aeabi_idivmod
|
||||
; EABI: mov [[div:r[0-9]+]], r0
|
||||
; EABI: mov [[rem:r[0-9]+]], r1
|
||||
; GNU: __aeabi_idiv
|
||||
; GNU: mov [[sum:r[0-9]+]], r0
|
||||
; GNU: __modsi3
|
||||
; GNU: add [[sum]]{{.*}}r0
|
||||
; GNU: __aeabi_idivmod
|
||||
; DARWIN: ___divsi3
|
||||
; DARWIN: mov [[sum:r[0-9]+]], r0
|
||||
; DARWIN: __modsi3
|
||||
@ -66,7 +60,7 @@ entry:
|
||||
%add = add nsw i32 %rem, %div
|
||||
%add2 = add nsw i32 %add, %rem1
|
||||
; EABI: add r0{{.*}}r1
|
||||
; GNU: add r0{{.*}}[[sum]]
|
||||
; GNU: add r0{{.*}}
|
||||
; DARWIN: add r0{{.*}}[[sum]]
|
||||
ret i32 %add2
|
||||
}
|
||||
@ -79,10 +73,7 @@ entry:
|
||||
%div = udiv i32 %a, %b
|
||||
%rem = urem i32 %a, %b
|
||||
; EABI: __aeabi_uidivmod
|
||||
; GNU: __aeabi_uidiv
|
||||
; GNU: mov [[sum:r[0-9]+]], r0
|
||||
; GNU: __umodsi3
|
||||
; GNU: add [[sum]]{{.*}}r0
|
||||
; GNU: __aeabi_uidivmod
|
||||
; DARWIN: ___udivsi3
|
||||
; DARWIN: mov [[sum:r[0-9]+]], r0
|
||||
; DARWIN: __umodsi3
|
||||
@ -94,7 +85,7 @@ entry:
|
||||
%add = add nuw i32 %rem, %div
|
||||
%add2 = add nuw i32 %add, %rem1
|
||||
; EABI: add r0{{.*}}r1
|
||||
; GNU: add r0{{.*}}[[sum]]
|
||||
; GNU: add r0{{.*}}
|
||||
; DARWIN: add r0{{.*}}[[sum]]
|
||||
ret i32 %add2
|
||||
}
|
||||
@ -131,15 +122,13 @@ entry:
|
||||
%div = sdiv i32 %a, %b
|
||||
%rem = srem i32 %a, %b
|
||||
; EABI: __aeabi_idivmod
|
||||
; GNU: __aeabi_idiv
|
||||
; GNU: mov [[sum:r[0-9]+]], r0
|
||||
; GNU: __modsi3
|
||||
; GNU: __aeabi_idivmod
|
||||
; DARWIN: ___divsi3
|
||||
; DARWIN: mov [[sum:r[0-9]+]], r0
|
||||
; DARWIN: __modsi3
|
||||
%add = add nsw i32 %rem, %div
|
||||
; EABI: add r0{{.*}}r1
|
||||
; GNU: add r0{{.*}}[[sum]]
|
||||
; EABI: add r0{{.*}}r1
|
||||
; GNU: add r0{{.*}}r1
|
||||
; DARWIN: add r0{{.*}}[[sum]]
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user