6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Sanity check MSRi for invalid mask values and reject it as invalid.

Browse Source 
rdar://problem/9246844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-07 01:37:34 +00:00
parent 0e382192c1
commit f16f4e09ec
2 changed files with 17 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@@ -836,6 +836,11 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// MSRi take a mask, followed by one so_imm operand. The mask contains the
// R Bit in bit 4, and the special register fields in bits 3-0.
if (Opcode == ARM::MSRi) {
// A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
// The hints instructions have more specific encodings, so if mask == 0,
// we should reject this as an invalid instruction.
if (slice(insn, 19, 16) == 0)
return false;
MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
slice(insn, 19, 16) /* Special Reg */ ));
// SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.