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Also convert SUBREG_TO_REG to a KILL when relevant, like the other subreg

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instructions.

This does not affect codegen much because SUBREG_TO_REG is only used by X86 and
X86 does not use the register scavenger, but it prevents verifier errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106583 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-06-22 22:11:07 +00:00
parent a3a204664d
commit f175c5c828
1 changed files with 12 additions and 7 deletions
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19
lib/CodeGen/LowerSubregs.cpp
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@ -166,10 +166,10 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
MI->getOperand(1).isImm() && MI->getOperand(1).isImm() &&
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
unsigned InsReg = MI->getOperand(2).getReg(); unsigned InsReg = MI->getOperand(2).getReg();
unsigned InsSIdx = MI->getOperand(2).getSubReg(); assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
unsigned SubIdx = MI->getOperand(3).getImm(); unsigned SubIdx = MI->getOperand(3).getImm();
assert(SubIdx != 0 && "Invalid index for insert_subreg"); assert(SubIdx != 0 && "Invalid index for insert_subreg");
@ -182,13 +182,18 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
if (DstSubReg == InsReg && InsSIdx == 0) { if (DstSubReg == InsReg) {
// No need to insert an identify copy instruction. // No need to insert an identify copy instruction.
// Watch out for case like this: // Watch out for case like this:
// %RAX<def> = ... // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
// %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 // We must leave %RAX live.
// The first def is defining RAX, not EAX so the top bits were not if (DstReg != InsReg) {
// zero extended. MI->setDesc(TII->get(TargetOpcode::KILL));
MI->RemoveOperand(3); // SubIdx
MI->RemoveOperand(1); // Imm
DEBUG(dbgs() << "subreg: replace by: " << *MI);
return true;
}
DEBUG(dbgs() << "subreg: eliminated!"); DEBUG(dbgs() << "subreg: eliminated!");
} else { } else {
// Insert sub-register copy // Insert sub-register copy