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Get the cached subtarget off the MachineFunction rather than

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inquiring for a new one from the TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229999 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2015-02-20 08:24:37 +00:00
parent 3ce9f152e4
commit f179b3f1d9
8 changed files with 17 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMFrameLowering.cpp
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@@ -1864,7 +1864,7 @@ static const uint64_t kSplitStackAvailable = 256;
void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
unsigned Opcode; unsigned Opcode;
unsigned CFIIndex; unsigned CFIIndex;
const ARMSubtarget *ST = &MF.getTarget().getSubtarget<ARMSubtarget>(); const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
bool Thumb = ST->isThumb(); bool Thumb = ST->isThumb();
// Sadly, this currently doesn't support varargs, platforms other than // Sadly, this currently doesn't support varargs, platforms other than

2
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -70,7 +70,7 @@ public:
bool runOnMachineFunction(MachineFunction &MF) override { bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through. // Reset the subtarget each time through.
Subtarget = &MF.getTarget().getSubtarget<ARMSubtarget>(); Subtarget = &MF.getSubtarget<ARMSubtarget>();
SelectionDAGISel::runOnMachineFunction(MF); SelectionDAGISel::runOnMachineFunction(MF);
return true; return true;
} }

2
lib/Target/ARM/ARMInstrInfo.cpp
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@@ -93,7 +93,7 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI, void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
Reloc::Model RM) const { Reloc::Model RM) const {
MachineFunction &MF = *MI->getParent()->getParent(); MachineFunction &MF = *MI->getParent()->getParent();
const ARMSubtarget &Subtarget = MF.getTarget().getSubtarget<ARMSubtarget>(); const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
if (!Subtarget.useMovt(MF)) { if (!Subtarget.useMovt(MF)) {
if (RM == Reloc::PIC_) if (RM == Reloc::PIC_)

4
lib/Target/ARM/ARMMachineFunctionInfo.cpp
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@@ -14,8 +14,8 @@ using namespace llvm;
void ARMFunctionInfo::anchor() { } void ARMFunctionInfo::anchor() { }
ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF) ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
: isThumb(MF.getTarget().getSubtarget<ARMSubtarget>().isThumb()), : isThumb(MF.getSubtarget<ARMSubtarget>().isThumb()),
hasThumb2(MF.getTarget().getSubtarget<ARMSubtarget>().hasThumb2()), hasThumb2(MF.getSubtarget<ARMSubtarget>().hasThumb2()),
StByValParamsPadding(0), ArgRegsSaveSize(0), HasStackFrame(false), StByValParamsPadding(0), ArgRegsSaveSize(0), HasStackFrame(false),
RestoreSPFromFP(false), LRSpilledForFarJump(false), RestoreSPFromFP(false), LRSpilledForFarJump(false),
FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),

10
lib/Target/ARM/ARMRegisterInfo.td
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@@ -199,7 +199,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
// Thumb1 instructions that know how to use hi regs. // Thumb1 instructions that know how to use hi regs.
let AltOrders = [(add LR, GPR), (trunc GPR, 8)]; let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}]; }];
} }
@@ -209,7 +209,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}]; }];
} }
@@ -219,7 +219,7 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}]; }];
} }
@@ -237,7 +237,7 @@ def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>;
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}]; }];
} }
@@ -255,7 +255,7 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
let AltOrders = [(and tcGPR, tGPR)]; let AltOrders = [(and tcGPR, tGPR)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}]; }];
} }

9
lib/Target/ARM/ARMSelectionDAGInfo.cpp
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@@ -32,7 +32,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
bool isVolatile, bool AlwaysInline, bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo, MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const { MachinePointerInfo SrcPtrInfo) const {
const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget<ARMSubtarget>(); const ARMSubtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
// Do repeated 4-byte loads and stores. To be improved. // Do repeated 4-byte loads and stores. To be improved.
// This requires 4-byte alignment. // This requires 4-byte alignment.
if ((Align & 3) != 0) if ((Align & 3) != 0)
@@ -150,14 +151,14 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
SDValue Src, SDValue Size, SDValue Src, SDValue Size,
unsigned Align, bool isVolatile, unsigned Align, bool isVolatile,
MachinePointerInfo DstPtrInfo) const { MachinePointerInfo DstPtrInfo) const {
const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget<ARMSubtarget>(); const ARMSubtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
// Use default for non-AAPCS (or MachO) subtargets // Use default for non-AAPCS (or MachO) subtargets
if (!Subtarget.isAAPCS_ABI() || Subtarget.isTargetMachO() || if (!Subtarget.isAAPCS_ABI() || Subtarget.isTargetMachO() ||
Subtarget.isTargetWindows()) Subtarget.isTargetWindows())
return SDValue(); return SDValue();
const ARMTargetLowering &TLI = const ARMTargetLowering &TLI = *Subtarget.getTargetLowering();
*DAG.getTarget().getSubtarget<ARMSubtarget>().getTargetLowering();
TargetLowering::ArgListTy Args; TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry; TargetLowering::ArgListEntry Entry;

2
lib/Target/ARM/MLxExpansionPass.cpp
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@@ -381,7 +381,7 @@ bool MLxExpansion::runOnMachineFunction(MachineFunction &Fn) {
TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo()); TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
TRI = Fn.getSubtarget().getRegisterInfo(); TRI = Fn.getSubtarget().getRegisterInfo();
MRI = &Fn.getRegInfo(); MRI = &Fn.getRegInfo();
const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>(); const ARMSubtarget *STI = &Fn.getSubtarget<ARMSubtarget>();
isLikeA9 = STI->isLikeA9() || STI->isSwift(); isLikeA9 = STI->isLikeA9() || STI->isSwift();
isSwift = STI->isSwift(); isSwift = STI->isSwift();

2
lib/Target/ARM/Thumb1InstrInfo.cpp
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@@ -44,7 +44,7 @@ void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
bool KillSrc) const { bool KillSrc) const {
// Need to check the arch. // Need to check the arch.
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
const ARMSubtarget &st = MF.getTarget().getSubtarget<ARMSubtarget>(); const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
"Thumb1 can only copy GPR registers"); "Thumb1 can only copy GPR registers");