6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-08 19:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Update tests to not be as dependent on section numbers.

Browse Source 
Many of these predate llvm-readobj. With elf-dump we had to match
a relocation to symbol number and symbol number to symbol name or
section number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2015-04-15 15:59:37 +00:00
parent e3e5fcab94
commit f194367792
46 changed files with 55 additions and 91 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
View File

@@ -15,11 +15,6 @@
; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals
; OBJ: Sections [
; OBJ: Section {
; OBJ: Index: 4
; OBJ-NEXT: Name: .bss
; OBJ: Symbols [ ; OBJ: Symbols [
; OBJ: Symbol { ; OBJ: Symbol {
; OBJ: Name: array00 ; OBJ: Name: array00

2
test/CodeGen/PowerPC/mcm-obj-2.ll
View File

@@ -20,7 +20,7 @@ entry:
; accessing function-scoped variable si. ; accessing function-scoped variable si.
; ;
; CHECK: Relocations [ ; CHECK: Relocations [
; CHECK: Section (2) .rela.text { ; CHECK: Section {{.*}} .rela.text {
; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]

4
test/CodeGen/PowerPC/mcm-obj.ll
View File

@@ -22,12 +22,12 @@ entry:
; accessing external variable ei. ; accessing external variable ei.
; ;
; MEDIUM: Relocations [ ; MEDIUM: Relocations [
; MEDIUM: Section (2) .rela.text { ; MEDIUM: Section {{.*}} .rela.text {
; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
; ;
; LARGE: Relocations [ ; LARGE: Relocations [
; LARGE: Section (2) .rela.text { ; LARGE: Section {{.*}} .rela.text {
; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]

2
test/CodeGen/SPARC/tls.ll
View File

@@ -99,7 +99,7 @@ entry:
; v9abs-obj: ] ; v9abs-obj: ]
; pic-obj: Relocations [ ; pic-obj: Relocations [
; pic-obj: Section (2) .rela.text { ; pic-obj: Section {{.*}} .rela.text {
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4 ; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8 ; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 local_symbol 0x0 ; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 local_symbol 0x0

2
test/MC/AArch64/arm64-elf-reloc-condbr.s
View File

@@ -4,7 +4,7 @@
b.eq somewhere b.eq somewhere
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0 // OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0
// OBJ-NEXT: } // OBJ-NEXT: }
// OBJ-NEXT: ] // OBJ-NEXT: ]

2
test/MC/AArch64/elf-extern.s
View File

@@ -27,7 +27,7 @@ check_extern: // @check_extern
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy // CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy
// CHECK: } // CHECK: }
// CHECK: ] // CHECK: ]

2
test/MC/AArch64/elf-globaladdress.ll
View File

@@ -40,7 +40,7 @@ define void @address() {
; OBJ: } ; OBJ: }
; OBJ: Relocations [ ; OBJ: Relocations [
; OBJ: Section (2) .rela.text { ; OBJ: Section {{.*}} .rela.text {
; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8
; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8
; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16

2
test/MC/AArch64/elf-reloc-addsubimm.s
View File

@@ -4,7 +4,7 @@
add x2, x3, #:lo12:some_label add x2, x3, #:lo12:some_label
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0
// OBJ-NEXT: } // OBJ-NEXT: }
// OBJ-NEXT: ] // OBJ-NEXT: ]

2
test/MC/AArch64/elf-reloc-ldrlit.s
View File

@@ -7,7 +7,7 @@
prfm pldl3keep, some_label prfm pldl3keep, some_label
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0
// OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0
// OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0

2
test/MC/AArch64/elf-reloc-ldstunsimm.s
View File

@@ -8,7 +8,7 @@
str q0, [sp, #:lo12:some_label] str q0, [sp, #:lo12:some_label]
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_LDST8_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x0 R_AARCH64_LDST8_ABS_LO12_NC some_label 0x0
// OBJ-NEXT: 0x4 R_AARCH64_LDST16_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LDST16_ABS_LO12_NC some_label 0x0
// OBJ-NEXT: 0x8 R_AARCH64_LDST32_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LDST32_ABS_LO12_NC some_label 0x0

2
test/MC/AArch64/elf-reloc-movw.s
View File

@@ -23,7 +23,7 @@
movn x19, #:abs_g2_s:some_label movn x19, #:abs_g2_s:some_label
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_MOVW_UABS_G0 some_label 0x0 // OBJ-NEXT: 0x0 R_AARCH64_MOVW_UABS_G0 some_label 0x0
// OBJ-NEXT: 0x4 R_AARCH64_MOVW_UABS_G0_NC some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_MOVW_UABS_G0_NC some_label 0x0
// OBJ-NEXT: 0x8 R_AARCH64_MOVW_UABS_G1 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_MOVW_UABS_G1 some_label 0x0

2
test/MC/AArch64/elf-reloc-pcreladdressing.s
View File

@@ -8,7 +8,7 @@
ldr x0, [x5, #:got_lo12:some_label] ldr x0, [x5, #:got_lo12:some_label]
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0 // OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0
// OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0
// OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0

2
test/MC/AArch64/elf-reloc-tstb.s
View File

@@ -5,7 +5,7 @@
tbnz w3, #15, somewhere tbnz w3, #15, somewhere
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: 0x0 R_AARCH64_TSTBR14 somewhere 0x0
// OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0
// OBJ-NEXT: } // OBJ-NEXT: }

2
test/MC/AArch64/elf-reloc-uncondbrimm.s
View File

@@ -5,7 +5,7 @@
bl somewhere bl somewhere
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: Section {{.*}} .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0 // OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0
// OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0
// OBJ-NEXT: } // OBJ-NEXT: }

2
test/MC/AArch64/tls-relocs.s
View File

@@ -18,7 +18,7 @@
// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw // CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
// CHECK-ELF: Relocations [ // CHECK-ELF: Relocations [
// CHECK-ELF-NEXT: Section (2) .rela.text { // CHECK-ELF-NEXT: Section {{.*}} .rela.text {
// CHECK-ELF-NEXT: 0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]] // CHECK-ELF-NEXT: 0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]]
// CHECK-ELF-NEXT: 0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
// CHECK-ELF-NEXT: 0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]

1
test/MC/ARM/2010-11-30-reloc-movt.s
View File

@@ -34,6 +34,7 @@ barf: @ @barf
// CHECK-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB // CHECK-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB
// CHECK-NEXT: 0010: 0088BDE8 // CHECK-NEXT: 0010: 0088BDE8
// CHECK-NEXT: ) // CHECK-NEXT: )
// CHECK: Name: .rel.text
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: 0x4 R_ARM_MOVW_ABS_NC a // CHECK-NEXT: 0x4 R_ARM_MOVW_ABS_NC a
// CHECK-NEXT: 0x8 R_ARM_MOVT_ABS // CHECK-NEXT: 0x8 R_ARM_MOVT_ABS

6
test/MC/ARM/arm-elf-symver.s
View File

@@ -23,7 +23,7 @@ defined3:
global1: global1:
@ CHECK: Relocations [ @ CHECK: Relocations [
@ CHECK-NEXT: Section (2) .rel.text { @ CHECK-NEXT: Section {{.*}} .rel.text {
@ CHECK-NEXT: 0x0 R_ARM_ABS32 .text 0x0 @ CHECK-NEXT: 0x0 R_ARM_ABS32 .text 0x0
@ CHECK-NEXT: 0x4 R_ARM_ABS32 bar2@zed 0x0 @ CHECK-NEXT: 0x4 R_ARM_ABS32 bar2@zed 0x0
@ CHECK-NEXT: 0x8 R_ARM_ABS32 .text 0x0 @ CHECK-NEXT: 0x8 R_ARM_ABS32 .text 0x0
@@ -93,7 +93,7 @@ global1:
@ CHECK-NEXT: Binding: Local (0x0) @ CHECK-NEXT: Binding: Local (0x0)
@ CHECK-NEXT: Type: Section (0x3) @ CHECK-NEXT: Type: Section (0x3)
@ CHECK-NEXT: Other: 0 @ CHECK-NEXT: Other: 0
@ CHECK-NEXT: Section: .data (0x3) @ CHECK-NEXT: Section: .data
@ CHECK-NEXT: } @ CHECK-NEXT: }
@ CHECK-NEXT: Symbol { @ CHECK-NEXT: Symbol {
@ CHECK-NEXT: Name: .bss (0) @ CHECK-NEXT: Name: .bss (0)
@@ -102,7 +102,7 @@ global1:
@ CHECK-NEXT: Binding: Local (0x0) @ CHECK-NEXT: Binding: Local (0x0)
@ CHECK-NEXT: Type: Section (0x3) @ CHECK-NEXT: Type: Section (0x3)
@ CHECK-NEXT: Other: 0 @ CHECK-NEXT: Other: 0
@ CHECK-NEXT: Section: .bss (0x4) @ CHECK-NEXT: Section: .bss
@ CHECK-NEXT: } @ CHECK-NEXT: }
@ CHECK-NEXT: Symbol { @ CHECK-NEXT: Symbol {
@ CHECK-NEXT: Name: g1@@zed @ CHECK-NEXT: Name: g1@@zed

6
test/MC/ARM/elf-movt.s
View File

@@ -35,9 +35,9 @@ barf: @ @barf
@ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3 @ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3
@ OBJ-NEXT: ) @ OBJ-NEXT: )
@ OBJ-NEXT: } @ OBJ-NEXT: }
@ OBJ-NEXT: Section { @ OBJ: Section {
@ OBJ-NEXT: Index: 2 @ OBJ: Index:
@ OBJ-NEXT: Name: .rel.text (1) @ OBJ: Name: .rel.text
@ OBJ-NEXT: Type: SHT_REL (0x9) @ OBJ-NEXT: Type: SHT_REL (0x9)
@ OBJ-NEXT: Flags [ (0x0) @ OBJ-NEXT: Flags [ (0x0)
@ OBJ-NEXT: ] @ OBJ-NEXT: ]

2
test/MC/ARM/elf-reloc-01.ll
View File

@@ -61,7 +61,7 @@ bb3: ; preds = %bb, %entry
declare void @exit(i32) noreturn nounwind declare void @exit(i32) noreturn nounwind
; OBJ: Relocations [ ; OBJ: Relocations [
; OBJ: Section (2) .rel.text { ; OBJ: Section {{.*}} .rel.text {
; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals ; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals
; OBJ: } ; OBJ: }
; OBJ: ] ; OBJ: ]

2
test/MC/ARM/elf-reloc-02.ll
View File

@@ -42,7 +42,7 @@ declare i32 @write(...)
declare void @exit(i32) noreturn nounwind declare void @exit(i32) noreturn nounwind
;; OBJ: Relocations [ ;; OBJ: Relocations [
;; OBJ: Section (2) .rel.text { ;; OBJ: Section {{.*}} .rel.text {
;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str ;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str
;; OBJ: } ;; OBJ: }
;; OBJ: ] ;; OBJ: ]

2
test/MC/ARM/elf-reloc-03.ll
View File

@@ -89,7 +89,7 @@ entry:
declare void @exit(i32) noreturn nounwind declare void @exit(i32) noreturn nounwind
;; OBJ: Relocations [ ;; OBJ: Relocations [
;; OBJ: Section (2) .rel.text { ;; OBJ: Section {{.*}} .rel.text {
;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable ;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable
;; OBJ: } ;; OBJ: }
;; OBJ: ] ;; OBJ: ]

2
test/MC/ARM/elf-reloc-condcall.s
View File

@@ -8,7 +8,7 @@
b some_label b some_label
// OBJ: Relocations [ // OBJ: Relocations [
// OBJ-NEXT: Section (2) .rel.text { // OBJ-NEXT: Section {{.*}} .rel.text {
// OBJ-NEXT: 0x0 R_ARM_JUMP24 some_label 0x0 // OBJ-NEXT: 0x0 R_ARM_JUMP24 some_label 0x0
// OBJ-NEXT: 0x4 R_ARM_CALL some_label 0x0 // OBJ-NEXT: 0x4 R_ARM_CALL some_label 0x0
// OBJ-NEXT: 0x8 R_ARM_CALL some_label 0x0 // OBJ-NEXT: 0x8 R_ARM_CALL some_label 0x0

4
test/MC/ARM/elf-thumbfunc-reloc.ll
View File

@@ -29,10 +29,10 @@ entry:
; CHECK: ] ; CHECK: ]
; CHECK: Relocations [ ; CHECK: Relocations [
; CHECK-NEXT: Section (2) .rel.text { ; CHECK-NEXT: Section {{.*}} .rel.text {
; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0 ; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: Section (7) .rel.ARM.exidx { ; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx {
; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0 ; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0
; CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0 ; CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0
; CHECK-NEXT: } ; CHECK-NEXT: }

2
test/MC/ARM/elf-thumbfunc-reloc.s
View File

@@ -22,7 +22,7 @@ ptr:
@@ make sure an R_ARM_THM_CALL relocation is generated for the call to g @@ make sure an R_ARM_THM_CALL relocation is generated for the call to g
@CHECK: Relocations [ @CHECK: Relocations [
@CHECK-NEXT: Section (2) .rel.text { @CHECK-NEXT: Section {{.*}} .rel.text {
@CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0 @CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0
@CHECK-NEXT: } @CHECK-NEXT: }

2
test/MC/ELF/basic-elf-32.s
View File

@@ -45,7 +45,7 @@ main: # @main
// CHECK: Name: .rel.text // CHECK: Name: .rel.text
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rel.text { // CHECK: Section {{.*}} .rel.text {
// CHECK: 0x6 R_386_32 .L.str1 // CHECK: 0x6 R_386_32 .L.str1
// CHECK: 0xB R_386_PC32 puts // CHECK: 0xB R_386_PC32 puts
// CHECK: 0x12 R_386_32 .L.str2 // CHECK: 0x12 R_386_32 .L.str2

2
test/MC/ELF/basic-elf-64.s
View File

@@ -45,7 +45,7 @@ main: # @main
// CHECK: Name: .rela.text // CHECK: Name: .rela.text
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK: 0x5 R_X86_64_32 .rodata.str1.1 0x0 // CHECK: 0x5 R_X86_64_32 .rodata.str1.1 0x0
// CHECK: 0xA R_X86_64_PC32 puts 0xFFFFFFFFFFFFFFFC // CHECK: 0xA R_X86_64_PC32 puts 0xFFFFFFFFFFFFFFFC
// CHECK: 0xF R_X86_64_32 .rodata.str1.1 0x6 // CHECK: 0xF R_X86_64_32 .rodata.str1.1 0x6

2
test/MC/ELF/common.s
View File

@@ -45,7 +45,7 @@
// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: Object // CHECK-NEXT: Type: Object
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .bss (0x4) // CHECK-NEXT: Section: .bss
// CHECK-NEXT: } // CHECK-NEXT: }

1
test/MC/ELF/compression.s
View File

@@ -10,7 +10,6 @@
// Check for the 'ZLIB' file magic at the start of the section only // Check for the 'ZLIB' file magic at the start of the section only
// CHECK-NEXT: ZLIB // CHECK-NEXT: ZLIB
// CHECK-NOT: ZLIB // CHECK-NOT: ZLIB
// CHECK: Contents of
// Don't compress small sections, such as this simple debug_abbrev example // Don't compress small sections, such as this simple debug_abbrev example
// CHECK: Contents of section .debug_abbrev: // CHECK: Contents of section .debug_abbrev:

2
test/MC/ELF/ifunc-reloc.s
View File

@@ -10,7 +10,7 @@ alias:
callq sym callq sym
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section (2) .rela.text { // CHECK-NEXT: Section {{.*}} .rela.text {
// CHECK-NEXT: 0x1 R_X86_64_PC32 sym 0xFFFFFFFFFFFFFFFC // CHECK-NEXT: 0x1 R_X86_64_PC32 sym 0xFFFFFFFFFFFFFFFC
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]

2
test/MC/ELF/local-reloc.s
View File

@@ -7,7 +7,7 @@
foo: foo:
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}}
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]

2
test/MC/ELF/merge.s
View File

@@ -21,7 +21,7 @@ zed:
foo: foo:
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section (2) .rela.text { // CHECK-NEXT: Section {{.*}} .rela.text {
// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PC32 .Lfoo 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PC32 .Lfoo 0x{{[^ ]+}}
// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .sec1 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .sec1 0x{{[^ ]+}}
// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .Lfoo 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .Lfoo 0x{{[^ ]+}}

6
test/MC/ELF/relocation-386.s
View File

@@ -4,7 +4,7 @@
// correctly point to the section or the symbol. // correctly point to the section or the symbol.
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section (2) .rel.text { // CHECK-NEXT: Section {{.*}} .rel.text {
// CHECK-NEXT: 0x2 R_386_GOTOFF .Lfoo 0x0 // CHECK-NEXT: 0x2 R_386_GOTOFF .Lfoo 0x0
// CHECK-NEXT: 0x{{[^ ]+}} R_386_PLT32 bar2 0x0 // CHECK-NEXT: 0x{{[^ ]+}} R_386_PLT32 bar2 0x0
// CHECK-NEXT: 0x{{[^ ]+}} R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 // CHECK-NEXT: 0x{{[^ ]+}} R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0
@@ -79,7 +79,7 @@
// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: TLS // CHECK-NEXT: Type: TLS
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: zedsec (0x5) // CHECK-NEXT: Section: zedsec
// CHECK-NEXT: } // CHECK-NEXT: }
// Symbol 7 is section 4 // Symbol 7 is section 4
// CHECK: Symbol { // CHECK: Symbol {
@@ -89,7 +89,7 @@
// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: Section // CHECK-NEXT: Type: Section
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .bss (0x4) // CHECK-NEXT: Section: .bss
// CHECK-NEXT: } // CHECK-NEXT: }
.text .text

4
test/MC/ELF/relocation-pc.s
View File

@@ -13,8 +13,8 @@
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: Section { // CHECK: Section {
// CHECK: Index: 2 // CHECK: Index:
// CHECK-NEXT: Name: .rela.text // CHECK: Name: .rela.text
// CHECK-NEXT: Type: SHT_RELA // CHECK-NEXT: Type: SHT_RELA
// CHECK-NEXT: Flags [ // CHECK-NEXT: Flags [
// CHECK-NEXT: ] // CHECK-NEXT: ]

35
test/MC/ELF/rename.s
View File

@@ -15,28 +15,9 @@ defined3:
.global defined1 .global defined1
// Section 1 is .text
// CHECK: Section { // CHECK: Section {
// CHECK: Index: 1 // CHECK: Index:
// CHECK-NEXT: Name: .text // CHECK: Name: .rela.text
// CHECK-NEXT: Type: SHT_PROGBITS
// CHECK-NEXT: Flags [
// CHECK-NEXT: SHF_ALLOC
// CHECK-NEXT: SHF_EXECINSTR
// CHECK-NEXT: ]
// CHECK-NEXT: Address: 0x0
// CHECK-NEXT: Offset: 0x40
// CHECK-NEXT: Size: 4
// CHECK-NEXT: Link: 0
// CHECK-NEXT: Info: 0
// CHECK-NEXT: AddressAlignment: 4
// CHECK-NEXT: EntrySize: 0
// CHECK-NEXT: Relocations [
// CHECK-NEXT: ]
// CHECK-NEXT: }
// CHECK-NEXT: Section {
// CHECK-NEXT: Index: 2
// CHECK-NEXT: Name: .rela.text (1)
// CHECK-NEXT: Type: SHT_RELA (0x4) // CHECK-NEXT: Type: SHT_RELA (0x4)
// CHECK-NEXT: Flags [ (0x0) // CHECK-NEXT: Flags [ (0x0)
// CHECK-NEXT: ] // CHECK-NEXT: ]
@@ -51,15 +32,3 @@ defined3:
// CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 // CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0
// CHECK-NEXT: ] // CHECK-NEXT: ]
// CHECK-NEXT: } // CHECK-NEXT: }
// Symbol 2 is section 1
// CHECK: Symbol {
// CHECK: Name: .text (0)
// CHECK-NEXT: Value: 0x0
// CHECK-NEXT: Size: 0
// CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: Section
// CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .text (0x1)
// CHECK-NEXT: }

2
test/MC/ELF/section-sym2.s
View File

@@ -6,7 +6,7 @@ mov .rodata, %rsi
.section .rodata .section .rodata
// CHECK:Relocations [ // CHECK:Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK: Relocation { // CHECK: Relocation {
// CHECK: Offset: 0x4 // CHECK: Offset: 0x4
// CHECK: Type: R_X86_64_32S (11) // CHECK: Type: R_X86_64_32S (11)

2
test/MC/ELF/symver-msvc.s
View File

@@ -11,7 +11,7 @@
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section (2) .rela.text { // CHECK-NEXT: Section {{.*}} .rela.text {
// CHECK-NEXT: 0x0 R_X86_64_32 ??_R0?AVexception@std@@@8 0x0 // CHECK-NEXT: 0x0 R_X86_64_32 ??_R0?AVexception@std@@@8 0x0
// CHECK-NEXT: 0x4 R_X86_64_32 @??_R0?AVinvalid_argument@std@@@8 0x0 // CHECK-NEXT: 0x4 R_X86_64_32 @??_R0?AVinvalid_argument@std@@@8 0x0
// CHECK-NEXT: 0x8 R_X86_64_32 __imp_??_R0?AVlogic_error@std@@@8 0x0 // CHECK-NEXT: 0x8 R_X86_64_32 __imp_??_R0?AVlogic_error@std@@@8 0x0

2
test/MC/ELF/symver.s
View File

@@ -22,7 +22,7 @@ defined3:
global1: global1:
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section (2) .rela.text { // CHECK-NEXT: Section {{.*}} .rela.text {
// CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 // CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0
// CHECK-NEXT: 0x4 R_X86_64_32 bar2@zed 0x0 // CHECK-NEXT: 0x4 R_X86_64_32 bar2@zed 0x0
// CHECK-NEXT: 0x8 R_X86_64_32 .text 0x0 // CHECK-NEXT: 0x8 R_X86_64_32 .text 0x0

2
test/MC/ELF/tls.s
View File

@@ -19,7 +19,7 @@ foobar:
// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: TLS // CHECK-NEXT: Type: TLS
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .zed (0x5) // CHECK-NEXT: Section: .zed
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: Symbol { // CHECK: Symbol {

4
test/MC/ELF/weakref.s
View File

@@ -131,7 +131,7 @@ bar15:
// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: Section // CHECK-NEXT: Type: Section
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .data (0x3) // CHECK-NEXT: Section: .data
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: Symbol { // CHECK-NEXT: Symbol {
// CHECK-NEXT: Name: .bss // CHECK-NEXT: Name: .bss
@@ -140,7 +140,7 @@ bar15:
// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: Section // CHECK-NEXT: Type: Section
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .bss (0x4) // CHECK-NEXT: Section: .bss
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: Symbol { // CHECK-NEXT: Symbol {
// CHECK-NEXT: Name: bar10 // CHECK-NEXT: Name: bar10

2
test/MC/Mips/elf-tls.s
View File

@@ -3,7 +3,7 @@
// Check that the appropriate relocations were created. // Check that the appropriate relocations were created.
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rel.text { // CHECK: Section {{.*}} .rel.text {
// CHECK: R_MIPS_TLS_LDM // CHECK: R_MIPS_TLS_LDM
// CHECK: R_MIPS_TLS_DTPREL_HI16 // CHECK: R_MIPS_TLS_DTPREL_HI16
// CHECK: R_MIPS_TLS_DTPREL_LO16 // CHECK: R_MIPS_TLS_DTPREL_LO16

2
test/MC/PowerPC/ppc-reloc.s
View File

@@ -12,7 +12,7 @@ foo:
.size foo, . - foo .size foo, . - foo
# CHECK: Relocations [ # CHECK: Relocations [
# CHECK-NEXT: Section (2) .rela.text { # CHECK-NEXT: Section {{.*}} .rela.text {
# CHECK-NEXT: 0x0 R_PPC_PLTREL24 printf 0x0 # CHECK-NEXT: 0x0 R_PPC_PLTREL24 printf 0x0
# CHECK-NEXT: 0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC # CHECK-NEXT: 0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC
# CHECK-NEXT: } # CHECK-NEXT: }

2
test/MC/PowerPC/tls-gd-obj.s
View File

@@ -47,7 +47,7 @@ a:
// for the call to __tls_get_addr. // for the call to __tls_get_addr.
// //
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSGD a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSGD a

2
test/MC/PowerPC/tls-ie-obj.s
View File

@@ -36,7 +36,7 @@ main: # @main
// accessing external variable a. // accessing external variable a.
// //
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA a
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLS a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLS a

2
test/MC/PowerPC/tls-ld-obj.s
View File

@@ -50,7 +50,7 @@ a:
// __tls_get_addr. // __tls_get_addr.
// //
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a
// CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSLD a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSLD a

2
test/MC/X86/expand-var.s
View File

@@ -1,6 +1,6 @@
// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux < %s | llvm-readobj -r | FileCheck %s // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux < %s | llvm-readobj -r | FileCheck %s
// CHECK: Section (2) .rela.text { // CHECK: Section {{.*}} .rela.text {
// CHECK-NEXT: 0x0 R_X86_64_32 d 0x0 // CHECK-NEXT: 0x0 R_X86_64_32 d 0x0
// CHECK-NEXT: } // CHECK-NEXT: }

2
test/MC/X86/reloc-undef-global.s
View File

@@ -7,7 +7,7 @@ bar = foo + 4
.long bar .long bar
// ELF: Relocations [ // ELF: Relocations [
// ELF-NEXT: Section (2) .rela.text { // ELF-NEXT: Section {{.*}} .rela.text {
// ELF-NEXT: 0x0 R_X86_64_32 foo 0x4 // ELF-NEXT: 0x0 R_X86_64_32 foo 0x4
// ELF-NEXT: } // ELF-NEXT: }
// ELF-NEXT: ] // ELF-NEXT: ]