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DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.
Fixes PR16083. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1162,7 +1162,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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}
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// Make sure we're not losing bits from the constant.
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if (MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
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if (MinBits > 0 &&
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MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
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EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
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if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
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// Will get folded away.
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@ -50,3 +50,19 @@ if.end:
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; CHECK: test3:
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; CHECK: cmpb $-1, %{{dil|cl}}
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}
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; PR16083
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define i1 @test4(i64 %a, i32 %b) {
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entry:
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%tobool = icmp ne i32 %b, 0
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br i1 %tobool, label %lor.end, label %lor.rhs
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lor.rhs: ; preds = %entry
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%and = and i64 0, %a
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%tobool1 = icmp ne i64 %and, 0
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %entry
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%p = phi i1 [ true, %entry ], [ %tobool1, %lor.rhs ]
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ret i1 %p
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}
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