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implement a trivial readme entry.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2007-11-27 22:36:16 +00:00
parent 789db09cde
commit f1b1c5ed1a
3 changed files with 26 additions and 18 deletions
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24
lib/Target/ARM/ARMISelLowering.cpp
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@ -262,6 +262,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// We have target-specific dag combine patterns for the following nodes:
// ARMISD::FMRRD - No need to call setTargetDAGCombine
setStackPointerRegisterToSaveRestore(ARM::SP); setStackPointerRegisterToSaveRestore(ARM::SP);
setSchedulingPreference(SchedulingForRegPressure); setSchedulingPreference(SchedulingForRegPressure);
setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
@ -1510,6 +1513,27 @@ ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
// ARM Optimization Hooks // ARM Optimization Hooks
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
static SDOperand PerformFMRRDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// fmrrd(fmdrr x, y) -> x,y
SDOperand InDouble = N->getOperand(0);
if (InDouble.getOpcode() == ARMISD::FMDRR)
return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
return SDOperand();
}
SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
switch (N->getOpcode()) {
default: break;
case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
}
return SDOperand();
}
/// isLegalAddressImmediate - Return true if the integer value can be used /// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the /// as the offset of the target addressing mode for load / store of the
/// given type. /// given type.

2
lib/Target/ARM/ARMISelLowering.h
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@ -78,6 +78,8 @@ namespace llvm {
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG); virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual const char *getTargetNodeName(unsigned Opcode) const; virtual const char *getTargetNodeName(unsigned Opcode) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,

18
lib/Target/ARM/README.txt
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@ -574,21 +574,3 @@ __Z11no_overflowjj:
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
Easy ARM microoptimization (with -mattr=+vfp2):
define i64 @i(double %X) {
%Y = bitcast double %X to i64
ret i64 %Y
}
compiles into:
_i:
fmdrr d0, r0, r1
fmrrd r0, r1, d0
bx lr
This just needs a target-specific dag combine to merge the two ARMISD nodes.
//===---------------------------------------------------------------------===//