From f1b4917f1beacd58fa6896ed40843a67d3edd9f8 Mon Sep 17 00:00:00 2001
From: Colin LeMahieu <colinl@codeaurora.org>
Date: Thu, 29 Jan 2015 16:55:37 +0000
Subject: [PATCH] [Hexagon] Adding CR intrinsic tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227463 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/HexagonIntrinsicsV4.td | 26 ++++++++
 test/CodeGen/Hexagon/intrinsics/cr.ll     | 76 +++++++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 test/CodeGen/Hexagon/intrinsics/cr.ll

diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV4.td b/lib/Target/Hexagon/HexagonIntrinsicsV4.td
index 4b1cf3f4c02..17571d3ee3e 100644
--- a/lib/Target/Hexagon/HexagonIntrinsicsV4.td
+++ b/lib/Target/Hexagon/HexagonIntrinsicsV4.td
@@ -131,12 +131,38 @@ def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
 *            ALU32/PRED                                             *
 *********************************************************************/
 
+// Compare
+def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s10ExtPred>;
+def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s10ExtPred>;
+def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u9ExtPred>;
+
 def: T_RR_pat<A4_rcmpeq,  int_hexagon_A4_rcmpeq>;
 def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
 
 def: T_RI_pat<A4_rcmpeqi,  int_hexagon_A4_rcmpeqi>;
 def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
 
+/********************************************************************
+*            CR                                                     *
+*********************************************************************/
+
+// CR / Logical Operations On Predicates.
+
+class qi_CRInst_qiqiqi_pat<Intrinsic IntID, InstHexagon Inst> :
+  Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt, IntRegs:$Ru)),
+      (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs),
+                           (C2_tfrrp IntRegs:$Rt),
+                           (C2_tfrrp IntRegs:$Ru))))>;
+
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_and,   C4_and_and>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_andn,  C4_and_andn>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_or,    C4_and_or>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_orn,   C4_and_orn>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_and,    C4_or_and>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_andn,   C4_or_andn>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_or,     C4_or_or>;
+def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_orn,    C4_or_orn>;
+
 /********************************************************************
 *            XTYPE/ALU                                              *
 *********************************************************************/
diff --git a/test/CodeGen/Hexagon/intrinsics/cr.ll b/test/CodeGen/Hexagon/intrinsics/cr.ll
new file mode 100644
index 00000000000..f0d6da560f3
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/cr.ll
@@ -0,0 +1,76 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Hexagon Programmer's Reference Manual 11.2 CR
+
+; Corner detection acceleration
+declare i32 @llvm.hexagon.C4.fastcorner9(i32, i32)
+define i32 @C4_fastcorner9(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = fastcorner9(r0, r1)
+
+declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
+define i32 @C4_fastcorner9_not(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = !fastcorner9(r0, r1)
+
+; Logical reductions on predicates
+declare i32 @llvm.hexagon.C2.any8(i32)
+define i32 @C2_any8(i32 %a) {
+  %z = call i32@llvm.hexagon.C2.any8(i32 %a)
+  ret i32 %z
+}
+; CHECK: p0 = any8(r0)
+
+declare i32 @llvm.hexagon.C2.all8(i32)
+define i32 @C2_all8(i32 %a) {
+  %z = call i32@llvm.hexagon.C2.all8(i32 %a)
+  ret i32 %z
+}
+
+; CHECK: p0 = all8(r0)
+
+; Logical operations on predicates
+declare i32 @llvm.hexagon.C2.and(i32, i32)
+define i32 @C2_and(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.and(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = and(r0, r1)
+
+declare i32 @llvm.hexagon.C2.or(i32, i32)
+define i32 @C2_or(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.or(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = or(r0, r1)
+
+declare i32 @llvm.hexagon.C2.xor(i32, i32)
+define i32 @C2_xor(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.xor(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = xor(r0, r1)
+
+declare i32 @llvm.hexagon.C2.andn(i32, i32)
+define i32 @C2_andn(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = and(r0, !r1)
+
+declare i32 @llvm.hexagon.C2.not(i32)
+define i32 @C2_not(i32 %a) {
+  %z = call i32@llvm.hexagon.C2.not(i32 %a)
+  ret i32 %z
+}
+; CHECK: p0 = not(r0)
+
+declare i32 @llvm.hexagon.C2.orn(i32, i32)
+define i32 @C2_orn(i32 %a, i32 %b) {
+  %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
+  ret i32 %z
+}
+; CHECK: p0 = or(r0, !r1)