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Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-22 18:22:06 +00:00
parent 88b7ccc7f0
commit f1c8e3e70e
2 changed files with 8 additions and 4 deletions
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8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1992,7 +1992,7 @@ static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
if (regs == 2) { if (regs == 2) {
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
} }
if (Rm == 0xD) { if (Rm != 0xF) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
} }
@ -2023,7 +2023,7 @@ static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
if (Rm == 0xD) { if (Rm != 0xF) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
} }
@ -2052,7 +2052,7 @@ static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
if (Rm == 0xD) { if (Rm != 0xF) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
} }
@ -2097,7 +2097,7 @@ static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
if (Rm == 0xD) { if (Rm != 0xF) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
} }

4
test/MC/Disassembler/ARM/neon.txt
View File

@ -1845,3 +1845,7 @@
# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
0x4f 0x1b 0xc0 0xf4 0x4f 0x1b 0xc0 0xf4
# CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
0x0 0xc 0xa0 0xf4
# CHECK: vld1.8 {d0[]}, [r0], r0