From f1d93ca920a106067d5773d57c85370a7efffe96 Mon Sep 17 00:00:00 2001
From: Bob Wilson <bob.wilson@apple.com>
Date: Fri, 9 Jul 2010 00:38:12 +0000
Subject: [PATCH] Reenable DAG combining for vector shuffles.  It looks like it
 was temporarily disabled and then never turned back on again.  Adjust some
 tests, one because this change avoids an unnecessary instruction, and the
 other to make it continue testing what it was intended to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |  2 --
 .../ARM/2010-06-29-PartialRedefFastAlloc.ll   | 21 +++++++++++--------
 test/CodeGen/ARM/reg_sequence.ll              |  1 -
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1641f56682d..17e6f430f4f 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6309,8 +6309,6 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
 }
 
 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
-  return SDValue();
-  
   EVT VT = N->getValueType(0);
   unsigned NumElts = VT.getVectorNumElements();
 
diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
index 389629e5966..bf0bb404172 100644
--- a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
+++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
@@ -4,19 +4,22 @@ target triple = "thumbv7-apple-darwin10"
 
 ; This tests the fast register allocator's handling of partial redefines:
 ;
-;	%reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0
-;	%reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1
+;      %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025...
+;      %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill>
 ;
-; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
-; it cannot also get %Q0.
+; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
+; redef, it cannot also get %Q0.
 
-; CHECK: vmov.i8 q0, #0x0
-; CHECK-NOT: vld1.64 {d0,d1}
+; CHECK: vld1.64 {d0, d1}, [r0]
+; CHECK-NOT: vld1.64 {d0, d1}
 ; CHECK: vmov.f64 d3, d0
 
-define i32 @main(i32 %argc, i8** %argv) nounwind {
+define i32 @test(i8* %arg) nounwind {
 entry:
- %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
- store <2 x i64> %0, <2 x i64>* undef, align 16
+ %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg)
+ %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>
+ store <2 x i64> %1, <2 x i64>* undef, align 16
  ret i32 undef
 }
+
+declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll
index b00020c3950..1c4552a4884 100644
--- a/test/CodeGen/ARM/reg_sequence.ll
+++ b/test/CodeGen/ARM/reg_sequence.ll
@@ -270,7 +270,6 @@ define arm_aapcs_vfpcc i32 @t10() nounwind {
 entry:
 ; CHECK: t10:
 ; CHECK: vmov.i32 q1, #0x3F000000
-; CHECK: vdup.32 q0, d0[0]
 ; CHECK: vmov d0, d1
 ; CHECK: vmla.f32 q0, q0, d0[0]
   %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]