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[AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).
This change only effects codegen when the constant is -3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231085 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6895,6 +6895,15 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
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N->getOperand(0));
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}
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} else {
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// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
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APInt VNP1 = -Value + 1;
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if (VNP1.isPowerOf2()) {
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SDValue ShiftedVal =
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DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
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DAG.getConstant(VNP1.logBase2(), MVT::i64));
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
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ShiftedVal);
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}
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// (mul x, -(2^N + 1)) => - (add (shl x, N), x)
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APInt VNM1 = -Value - 1;
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if (VNM1.isPowerOf2()) {
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@ -6905,15 +6914,6 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
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DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
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}
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// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
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APInt VNP1 = -Value + 1;
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if (VNP1.isPowerOf2()) {
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SDValue ShiftedVal =
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DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
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DAG.getConstant(VNP1.logBase2(), MVT::i64));
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
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ShiftedVal);
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}
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}
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}
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return SDValue();
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@ -74,8 +74,7 @@ define i32 @ntest2(i32 %x) {
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define i32 @ntest3(i32 %x) {
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; CHECK-LABEL: ntest3
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; CHECK: add {{w[0-9]+}}, w0, w0, lsl #1
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; CHECK: neg w0, {{w[0-9]+}}
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; CHECK: sub w0, w0, w0, lsl #2
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%mul = mul nsw i32 %x, -3
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ret i32 %mul
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