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ARM updating VST2 pseudo-lowering fixed vs. register update.

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rdar://10663487

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147876 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-01-10 21:11:12 +00:00
parent e4ad582729
commit f1f16c832f
4 changed files with 17 additions and 8 deletions
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2
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -314,7 +314,7 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VST2d16PseudoWB_fixed, ARM::VST2d16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
{ ARM::VST2d16PseudoWB_register, ARM::VST2d16wb_register, false, true, true, SingleSpc, 2, 4 ,false},
{ ARM::VST2d32Pseudo, ARM::VST2d32, false, false, false, SingleSpc, 2, 2 ,false},
{ ARM::VST2d32PseudoWB_fixed, ARM::VST2d32wb_fixed, false, true, true, SingleSpc, 2, 2 ,false},
{ ARM::VST2d32PseudoWB_fixed, ARM::VST2d32wb_fixed, false, true, false, SingleSpc, 2, 2 ,false},
{ ARM::VST2d32PseudoWB_register, ARM::VST2d32wb_register, false, true, true, SingleSpc, 2, 2 ,false},
{ ARM::VST2d8Pseudo, ARM::VST2d8, false, false, false, SingleSpc, 2, 8 ,false},
{ ARM::VST2d8PseudoWB_fixed, ARM::VST2d8wb_fixed, false, true, false, SingleSpc, 2, 8 ,false},

2
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1822,7 +1822,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
Opc = getVLDSTRegisterUpdateOpcode(Opc);
// We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
// check for that explicitly too. Horribly hacky, but temporary.
if ((NumVecs != 1 && Opc != ARM::VST1q64PseudoWB_fixed) ||
if ((NumVecs > 2 && Opc != ARM::VST1q64PseudoWB_fixed) ||
!isa<ConstantSDNode>(Inc.getNode()))
Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
}

12
lib/Target/ARM/ARMInstrNEON.td
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@ -1673,12 +1673,12 @@ defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
def VST2d8PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
def VST2d16PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
def VST2d32PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
def VST2d8PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
def VST2d16PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
def VST2d32PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
def VST2d8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>;
def VST2d16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>;
def VST2d32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>;
def VST2d8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>;
def VST2d16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>;
def VST2d32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>;
def VST2q8PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
def VST2q16PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;

9
test/CodeGen/ARM/vst2.ll
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@ -110,6 +110,15 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
ret void
}
define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
;CHECK: vst2update
;CHECK: vst2.16 {d16, d17}, [r0]!
%tmp1 = load <4 x i16>* %B
tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
%t5 = getelementptr inbounds i8* %out, i32 16
ret i8* %t5
}
declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
declare void @llvm.arm.neon.vst2.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind
declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind