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Add missing const qualifiers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-29 18:35:22 +00:00
parent 2fb813d70b
commit f277ee4be7
4 changed files with 21 additions and 17 deletions
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9
include/llvm/CodeGen/MachineInstr.h
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@ -415,15 +415,16 @@ public:
/// findRegisterUseOperandIdx() - Returns the operand index that is a use of /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
/// the specific register or -1 if it is not found. It further tightening /// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true. /// the search criteria to a use that kills the register if isKill is true.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false); int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const;
/// findRegisterDefOperand() - Returns the MachineOperand that is a def of /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
/// the specific register or NULL if it is not found. /// the specific register or NULL if it is not found.
MachineOperand *findRegisterDefOperand(unsigned Reg); MachineOperand *findRegisterDefOperand(unsigned Reg);
/// findFirstPredOperand() - Find the first operand in the operand list that /// findFirstPredOperandIdx() - Find the index of the first operand in the
// is used to represent the predicate. /// operand list that is used to represent the predicate. It returns -1 if
MachineOperand *findFirstPredOperand(); /// none is found.
int findFirstPredOperandIdx() const;
/// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
/// ///

12
include/llvm/Target/TargetInstrInfo.h
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@ -395,19 +395,21 @@ public:
/// isPredicable - Returns true if the instruction is already predicated. /// isPredicable - Returns true if the instruction is already predicated.
/// ///
virtual bool isPredicated(MachineInstr *MI) const { virtual bool isPredicated(const MachineInstr *MI) const {
return false; return false;
} }
/// PredicateInstruction - Convert the instruction into a predicated /// PredicateInstruction - Convert the instruction into a predicated
/// instruction. It returns true if the operation was successful. /// instruction. It returns true if the operation was successful.
virtual bool PredicateInstruction(MachineInstr *MI, virtual
std::vector<MachineOperand> &Pred) const; bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const;
/// SubsumesPredicate - Returns true if the first specified predicated /// SubsumesPredicate - Returns true if the first specified predicated
/// subsumes the second, e.g. GE subsumes GT. /// subsumes the second, e.g. GE subsumes GT.
virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1, virtual
std::vector<MachineOperand> &Pred2) const { bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
const std::vector<MachineOperand> &Pred2) const {
return false; return false;
} }

15
lib/CodeGen/MachineInstr.cpp
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@ -191,9 +191,9 @@ bool MachineInstr::isPredicable() const {
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening /// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true. /// the search criteria to a use that kills the register if isKill is true.
int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) { int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i); const MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == Reg) if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
if (!isKill || MO.isKill()) if (!isKill || MO.isKill())
return i; return i;
@ -212,17 +212,18 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
return NULL; return NULL;
} }
/// findFirstPredOperand() - Find the first operand in the operand list that /// findFirstPredOperandIdx() - Find the index of the first operand in the
// is used to represent the predicate. /// operand list that is used to represent the predicate. It returns -1 if
MachineOperand *MachineInstr::findFirstPredOperand() { /// none is found.
int MachineInstr::findFirstPredOperandIdx() const {
const TargetInstrDescriptor *TID = getInstrDescriptor(); const TargetInstrDescriptor *TID = getInstrDescriptor();
if (TID->Flags & M_PREDICABLE) { if (TID->Flags & M_PREDICABLE) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
return &getOperand(i); return i;
} }
return NULL; return -1;
} }
/// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// copyKillDeadInfo - Copies kill / dead operand properties from MI.

2
lib/Target/TargetInstrInfo.cpp
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@ -61,7 +61,7 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
} }
bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI, bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const { const std::vector<MachineOperand> &Pred) const {
bool MadeChange = false; bool MadeChange = false;
const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_PREDICABLE) { if (TID->Flags & M_PREDICABLE) {