Rename MachineOptInfo to TargetoptInfo

Rename MachineCacheInfo to TargetCacheInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5203 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-12-29 02:50:35 +00:00
parent dde126207e
commit f27eeea54f
7 changed files with 22 additions and 23 deletions

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@@ -1,16 +1,16 @@
//===-- llvm/Target/MachineCacheInfo.h --------------------------*- C++ -*-===// //===-- llvm/Target/TargetCacheInfo.h ---------------------------*- C++ -*-===//
// //
// Describes properties of the target cache architecture. // Describes properties of the target cache architecture.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_MACHINECACHEINFO_H #ifndef LLVM_TARGET_TARGETCACHEINFO_H
#define LLVM_TARGET_MACHINECACHEINFO_H #define LLVM_TARGET_TARGETCACHEINFO_H
#include "Support/DataTypes.h" #include "Support/DataTypes.h"
class TargetMachine; class TargetMachine;
struct MachineCacheInfo : public NonCopyableV { struct TargetCacheInfo : public NonCopyableV {
const TargetMachine ⌖ const TargetMachine ⌖
protected: protected:
unsigned int numLevels; unsigned int numLevels;
@@ -19,7 +19,7 @@ protected:
std::vector<unsigned short> cacheAssoc; std::vector<unsigned short> cacheAssoc;
public: public:
MachineCacheInfo(const TargetMachine& tgt) : target(tgt) { TargetCacheInfo(const TargetMachine& tgt) : target(tgt) {
Initialize(); Initialize();
} }

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@@ -15,8 +15,8 @@ class MachineInstrDescriptor;
class MachineSchedInfo; class MachineSchedInfo;
class MachineRegInfo; class MachineRegInfo;
class TargetFrameInfo; class TargetFrameInfo;
class MachineCacheInfo; class TargetCacheInfo;
class MachineOptInfo; class TargetOptInfo;
class MachineCodeEmitter; class MachineCodeEmitter;
class MRegisterInfo; class MRegisterInfo;
class PassManager; class PassManager;
@@ -60,8 +60,8 @@ public:
virtual const MachineSchedInfo& getSchedInfo() const = 0; virtual const MachineSchedInfo& getSchedInfo() const = 0;
virtual const MachineRegInfo& getRegInfo() const = 0; virtual const MachineRegInfo& getRegInfo() const = 0;
virtual const TargetFrameInfo& getFrameInfo() const = 0; virtual const TargetFrameInfo& getFrameInfo() const = 0;
virtual const MachineCacheInfo& getCacheInfo() const = 0; virtual const TargetCacheInfo& getCacheInfo() const = 0;
virtual const MachineOptInfo& getOptInfo() const = 0; virtual const TargetOptInfo& getOptInfo() const = 0;
const TargetData &getTargetData() const { return DataLayout; } const TargetData &getTargetData() const { return DataLayout; }
/// getRegisterInfo - If register information is available, return it. If /// getRegisterInfo - If register information is available, return it. If

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@@ -1,20 +1,19 @@
//===-- llvm/Target/MachineOptInfo.h -----------------------------*- C++ -*-==// //===-- llvm/Target/TargetOptInfo.h ------------------------------*- C++ -*-==//
// //
// Describes properties of the target cache architecture.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_MACHINEOPTINFO_H #ifndef LLVM_TARGET_TARGETOPTINFO_H
#define LLVM_TARGET_MACHINEOPTINFO_H #define LLVM_TARGET_TARGETOPTINFO_H
#include "Support/DataTypes.h" #include "Support/DataTypes.h"
class TargetMachine; class TargetMachine;
struct MachineOptInfo : public NonCopyableV { struct TargetOptInfo : public NonCopyableV {
const TargetMachine &target; const TargetMachine &target;
public: public:
MachineOptInfo(const TargetMachine& tgt): target(tgt) { } TargetOptInfo(const TargetMachine& tgt): target(tgt) { }
virtual bool IsUselessCopy (const MachineInstr* MI) const = 0; virtual bool IsUselessCopy (const MachineInstr* MI) const = 0;
}; };

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@@ -14,7 +14,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/MachineCacheInfo.h" #include "llvm/Target/TargetCacheInfo.h"
#include "llvm/Function.h" #include "llvm/Function.h"
#include "llvm/iOther.h" #include "llvm/iOther.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"

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@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/MachineOptInfo.h" #include "llvm/Target/TargetOptInfo.h"
#include "llvm/BasicBlock.h" #include "llvm/BasicBlock.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"

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@@ -1,12 +1,12 @@
//===-- TargetMachine.cpp - General Target Information ---------------------==// //===-- TargetMachine.cpp - General Target Information ---------------------==//
// //
// This file describes the general parts of a Target machine. // This file describes the general parts of a Target machine.
// This file also implements MachineCacheInfo. // This file also implements TargetCacheInfo.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineCacheInfo.h" #include "llvm/Target/TargetCacheInfo.h"
#include "llvm/Type.h" #include "llvm/Type.h"
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
@@ -36,13 +36,13 @@ unsigned TargetMachine::findOptimalStorageSize(const Type *Ty) const {
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// class MachineCacheInfo // class TargetCacheInfo
// //
// Purpose: // Purpose:
// Describes properties of the target cache architecture. // Describes properties of the target cache architecture.
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
void MachineCacheInfo::Initialize() { void TargetCacheInfo::Initialize() {
numLevels = 2; numLevels = 2;
cacheLineSizes.push_back(16); cacheLineSizes.push_back(32); cacheLineSizes.push_back(16); cacheLineSizes.push_back(32);
cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20); cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20);

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@@ -25,8 +25,8 @@ public:
virtual const MachineSchedInfo &getSchedInfo() const { abort(); } virtual const MachineSchedInfo &getSchedInfo() const { abort(); }
virtual const MachineRegInfo &getRegInfo() const { abort(); } virtual const MachineRegInfo &getRegInfo() const { abort(); }
virtual const MachineCacheInfo &getCacheInfo() const { abort(); } virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
virtual const MachineOptInfo &getOptInfo() const { abort(); } virtual const TargetOptInfo &getOptInfo() const { abort(); }
/// addPassesToJITCompile - Add passes to the specified pass manager to /// addPassesToJITCompile - Add passes to the specified pass manager to
/// implement a fast dynamic compiler for this target. Return true if this is /// implement a fast dynamic compiler for this target. Return true if this is