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https://github.com/c64scene-ar/llvm-6502.git
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Merge load/store sequences with adresses: base + index + offset
We would also like to merge sequences that involve a variable index like in the
example below.
int index = *idx++
int i0 = c[index+0];
int i1 = c[index+1];
b[0] = i0;
b[1] = i1;
By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.
The dag for the code above will look something like:
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i8 load %index))))
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (add (i8 load %index)
(i8 1))))
vs
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
radar://13536387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
parent
4647919784
commit
f28a29b776
@ -7711,16 +7711,82 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
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return SDValue();
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}
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/// Returns the base pointer and an integer offset from that object.
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static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) {
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if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) {
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int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
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SDValue Base = Ptr->getOperand(0);
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return std::make_pair(Base, Offset);
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/// Helper struct to parse and store a memory address as base + index + offset.
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/// We ignore sign extensions when it is safe to do so.
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/// The following two expressions are not equivalent. To differentiate we need
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/// to store whether there was a sign extension involved in the index
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/// computation.
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/// (load (i64 add (i64 copyfromreg %c)
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/// (i64 signextend (add (i8 load %index)
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/// (i8 1))))
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/// vs
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///
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/// (load (i64 add (i64 copyfromreg %c)
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/// (i64 signextend (i32 add (i32 signextend (i8 load %index))
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/// (i32 1)))))
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struct BaseIndexOffset {
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SDValue Base;
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SDValue Index;
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int64_t Offset;
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bool IsIndexSignExt;
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BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
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BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
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bool IsIndexSignExt) :
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Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
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bool equalBaseIndex(const BaseIndexOffset &Other) {
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return Other.Base == Base && Other.Index == Index &&
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Other.IsIndexSignExt == IsIndexSignExt;
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}
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return std::make_pair(Ptr, 0);
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}
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/// Parses tree in Ptr for base, index, offset addresses.
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static BaseIndexOffset match(SDValue Ptr) {
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bool IsIndexSignExt = false;
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// Just Base or possibly anything else.
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if (Ptr->getOpcode() != ISD::ADD)
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// Base + offset.
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if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
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int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
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return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
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IsIndexSignExt);
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}
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// Look at Base + Index + Offset cases.
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SDValue Base = Ptr->getOperand(0);
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SDValue IndexOffset = Ptr->getOperand(1);
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// Skip signextends.
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if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
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IndexOffset = IndexOffset->getOperand(0);
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IsIndexSignExt = true;
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}
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// Either the case of Base + Index (no offset) or something else.
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if (IndexOffset->getOpcode() != ISD::ADD)
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return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
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// Now we have the case of Base + Index + offset.
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SDValue Index = IndexOffset->getOperand(0);
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SDValue Offset = IndexOffset->getOperand(1);
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if (!isa<ConstantSDNode>(Offset))
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// Ignore signextends.
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if (Index->getOpcode() == ISD::SIGN_EXTEND) {
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Index = Index->getOperand(0);
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IsIndexSignExt = true;
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} else IsIndexSignExt = false;
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int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
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return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
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}
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};
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/// Holds a pointer to an LSBaseSDNode as well as information on where it
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/// is located in a sequence of memory operations connected by a chain.
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@ -7767,16 +7833,16 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
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return false;
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// This holds the base pointer and the offset in bytes from the base pointer.
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std::pair<SDValue, int64_t> BasePtr =
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GetPointerBaseAndOffset(St->getBasePtr());
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// This holds the base pointer, index, and the offset in bytes from the base
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// pointer.
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BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
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// We must have a base and an offset.
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if (!BasePtr.first.getNode())
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if (!BasePtr.Base.getNode())
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return false;
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// Do not handle stores to undef base pointers.
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if (BasePtr.first.getOpcode() == ISD::UNDEF)
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if (BasePtr.Base.getOpcode() == ISD::UNDEF)
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return false;
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// Save the LoadSDNodes that we find in the chain.
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@ -7798,11 +7864,10 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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break;
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// Find the base pointer and offset for this memory node.
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std::pair<SDValue, int64_t> Ptr =
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GetPointerBaseAndOffset(Index->getBasePtr());
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BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
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// Check that the base pointer is the same as the original one.
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if (Ptr.first.getNode() != BasePtr.first.getNode())
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if (!Ptr.equalBaseIndex(BasePtr))
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break;
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// Check that the alignment is the same.
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@ -7828,7 +7893,7 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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break;
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// We found a potential memory operand to merge.
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StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
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StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
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// Find the next memory operand in the chain. If the next operand in the
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// chain is a store then move up and continue the scan with the next
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@ -8025,7 +8090,7 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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// Find acceptable loads. Loads need to have the same chain (token factor),
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// must not be zext, volatile, indexed, and they must be consecutive.
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SDValue LdBasePtr;
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BaseIndexOffset LdBasePtr;
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for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
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StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
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LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
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@ -8051,21 +8116,19 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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if (Ld->getMemoryVT() != MemVT)
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break;
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std::pair<SDValue, int64_t> LdPtr =
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GetPointerBaseAndOffset(Ld->getBasePtr());
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BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
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// If this is not the first ptr that we check.
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if (LdBasePtr.getNode()) {
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if (LdBasePtr.Base.getNode()) {
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// The base ptr must be the same.
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if (LdPtr.first != LdBasePtr)
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if (!LdPtr.equalBaseIndex(LdBasePtr))
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break;
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} else {
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// Check that all other base pointers are the same as this one.
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LdBasePtr = LdPtr.first;
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LdBasePtr = LdPtr;
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}
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// We found a potential memory operand to merge.
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LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0));
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LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
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}
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if (LoadNodes.size() < 2)
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@ -337,3 +337,99 @@ block4: ; preds = %4, %.lr.ph
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ret void
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}
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; Make sure that we merge the consecutive load/store sequence below and use a
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; word (16 bit) instead of a byte copy.
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; CHECK: MergeLoadStoreBaseIndexOffset
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; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
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; CHECK: movw [[REG]], (%{{.*}})
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define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) {
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br label %1
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; <label>:1
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%.09 = phi i32 [ %n, %0 ], [ %11, %1 ]
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%.08 = phi i8* [ %b, %0 ], [ %10, %1 ]
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%.0 = phi i64* [ %a, %0 ], [ %2, %1 ]
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%2 = getelementptr inbounds i64* %.0, i64 1
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%3 = load i64* %.0, align 1
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%4 = getelementptr inbounds i8* %c, i64 %3
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%5 = load i8* %4, align 1
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%6 = add i64 %3, 1
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%7 = getelementptr inbounds i8* %c, i64 %6
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%8 = load i8* %7, align 1
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store i8 %5, i8* %.08, align 1
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%9 = getelementptr inbounds i8* %.08, i64 1
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store i8 %8, i8* %9, align 1
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%10 = getelementptr inbounds i8* %.08, i64 2
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%11 = add nsw i32 %.09, -1
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%12 = icmp eq i32 %11, 0
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br i1 %12, label %13, label %1
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; <label>:13
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ret void
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}
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; Make sure that we merge the consecutive load/store sequence below and use a
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; word (16 bit) instead of a byte copy even if there are intermediate sign
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; extensions.
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; CHECK: MergeLoadStoreBaseIndexOffsetSext
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; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
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; CHECK: movw [[REG]], (%{{.*}})
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define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
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br label %1
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; <label>:1
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%.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
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%.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
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%.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
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%2 = getelementptr inbounds i8* %.0, i64 1
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%3 = load i8* %.0, align 1
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%4 = sext i8 %3 to i64
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%5 = getelementptr inbounds i8* %c, i64 %4
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%6 = load i8* %5, align 1
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%7 = add i64 %4, 1
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%8 = getelementptr inbounds i8* %c, i64 %7
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%9 = load i8* %8, align 1
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store i8 %6, i8* %.08, align 1
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%10 = getelementptr inbounds i8* %.08, i64 1
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store i8 %9, i8* %10, align 1
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%11 = getelementptr inbounds i8* %.08, i64 2
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%12 = add nsw i32 %.09, -1
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%13 = icmp eq i32 %12, 0
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br i1 %13, label %14, label %1
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; <label>:14
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ret void
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}
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; However, we can only merge ignore sign extensions when they are on all memory
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; computations;
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; CHECK: loadStoreBaseIndexOffsetSextNoSex
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; CHECK-NOT: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
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; CHECK-NOT: movw [[REG]], (%{{.*}})
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define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
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br label %1
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; <label>:1
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%.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
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%.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
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%.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
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%2 = getelementptr inbounds i8* %.0, i64 1
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%3 = load i8* %.0, align 1
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%4 = sext i8 %3 to i64
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%5 = getelementptr inbounds i8* %c, i64 %4
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%6 = load i8* %5, align 1
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%7 = add i8 %3, 1
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%wrap.4 = sext i8 %7 to i64
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%8 = getelementptr inbounds i8* %c, i64 %wrap.4
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%9 = load i8* %8, align 1
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store i8 %6, i8* %.08, align 1
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%10 = getelementptr inbounds i8* %.08, i64 1
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store i8 %9, i8* %10, align 1
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%11 = getelementptr inbounds i8* %.08, i64 2
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%12 = add nsw i32 %.09, -1
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%13 = icmp eq i32 %12, 0
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br i1 %13, label %14, label %1
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; <label>:14
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ret void
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}
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