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https://github.com/c64scene-ar/llvm-6502.git
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[asan] properly instrument memory accesses that have small alignment (smaller than min(8,size)) by making two checks instead of one. This may slowdown some cases, e.g. long long on 32-bit or wide loads produced after loop unrolling. The benefit is higher sencitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209508 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kostya Serebryany
parent
4f22c980f4
commit
f2938bf8da
@ -623,26 +623,31 @@ void AddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) {
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}
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// If I is an interesting memory access, return the PointerOperand
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// and set IsWrite. Otherwise return NULL.
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static Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite) {
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// and set IsWrite/Alignment. Otherwise return NULL.
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static Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
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unsigned *Alignment) {
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if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
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if (!ClInstrumentReads) return nullptr;
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*IsWrite = false;
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*Alignment = LI->getAlignment();
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return LI->getPointerOperand();
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}
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if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
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if (!ClInstrumentWrites) return nullptr;
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*IsWrite = true;
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*Alignment = SI->getAlignment();
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return SI->getPointerOperand();
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}
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if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) {
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if (!ClInstrumentAtomics) return nullptr;
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*IsWrite = true;
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*Alignment = 0;
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return RMW->getPointerOperand();
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}
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if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) {
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if (!ClInstrumentAtomics) return nullptr;
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*IsWrite = true;
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*Alignment = 0;
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return XCHG->getPointerOperand();
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}
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return nullptr;
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@ -692,7 +697,8 @@ AddressSanitizer::instrumentPointerComparisonOrSubtraction(Instruction *I) {
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void AddressSanitizer::instrumentMop(Instruction *I, bool UseCalls) {
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bool IsWrite = false;
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Value *Addr = isInterestingMemoryAccess(I, &IsWrite);
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unsigned Alignment = 0;
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Value *Addr = isInterestingMemoryAccess(I, &IsWrite, &Alignment);
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assert(Addr);
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if (ClOpt && ClOptGlobals) {
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if (GlobalVariable *G = dyn_cast<GlobalVariable>(Addr)) {
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@ -727,11 +733,14 @@ void AddressSanitizer::instrumentMop(Instruction *I, bool UseCalls) {
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else
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NumInstrumentedReads++;
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// Instrument a 1-, 2-, 4-, 8-, or 16- byte access with one check.
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if (TypeSize == 8 || TypeSize == 16 ||
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TypeSize == 32 || TypeSize == 64 || TypeSize == 128)
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unsigned Granularity = 1 << Mapping.Scale;
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// Instrument a 1-, 2-, 4-, 8-, or 16- byte access with one check
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// if the data is properly aligned.
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if ((TypeSize == 8 || TypeSize == 16 || TypeSize == 32 || TypeSize == 64 ||
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TypeSize == 128) &&
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(Alignment >= Granularity || Alignment == 0 || Alignment >= TypeSize / 8))
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return instrumentAddress(I, I, Addr, TypeSize, IsWrite, nullptr, UseCalls);
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// Instrument unusual size (but still multiple of 8).
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// Instrument unusual size or unusual alignment.
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// We can not do it with a single check, so we do 1-byte check for the first
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// and the last bytes. We call __asan_report_*_n(addr, real_size) to be able
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// to report the actual access size.
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@ -1328,6 +1337,7 @@ bool AddressSanitizer::runOnFunction(Function &F) {
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SmallVector<Instruction*, 16> PointerComparisonsOrSubtracts;
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int NumAllocas = 0;
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bool IsWrite;
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unsigned Alignment;
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// Fill the set of memory operations to instrument.
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for (Function::iterator FI = F.begin(), FE = F.end();
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@ -1338,7 +1348,7 @@ bool AddressSanitizer::runOnFunction(Function &F) {
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for (BasicBlock::iterator BI = FI->begin(), BE = FI->end();
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BI != BE; ++BI) {
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if (LooksLikeCodeInBug11395(BI)) return false;
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if (Value *Addr = isInterestingMemoryAccess(BI, &IsWrite)) {
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if (Value *Addr = isInterestingMemoryAccess(BI, &IsWrite, &Alignment)) {
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if (ClOpt && ClOptSameTemp) {
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if (!TempsToInstrument.insert(Addr))
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continue; // We've seen this temp in the current BB.
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@ -1390,7 +1400,7 @@ bool AddressSanitizer::runOnFunction(Function &F) {
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Instruction *Inst = ToInstrument[i];
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if (ClDebugMin < 0 || ClDebugMax < 0 ||
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(NumInstrumented >= ClDebugMin && NumInstrumented <= ClDebugMax)) {
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if (isInterestingMemoryAccess(Inst, &IsWrite))
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if (isInterestingMemoryAccess(Inst, &IsWrite, &Alignment))
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instrumentMop(Inst, UseCalls);
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else
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instrumentMemIntrinsic(cast<MemIntrinsic>(Inst));
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@ -34,7 +34,7 @@ define i32 @test_load(i32* %a) sanitize_address {
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entry:
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%tmp1 = load i32* %a
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%tmp1 = load i32* %a, align 4
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ret i32 %tmp1
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}
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@ -66,7 +66,7 @@ define void @test_store(i32* %a) sanitize_address {
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;
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entry:
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store i32 42, i32* %a
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store i32 42, i32* %a, align 4
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ret void
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}
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@ -115,6 +115,18 @@ define void @i40test(i40* %a, i40* %b) nounwind uwtable sanitize_address {
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; CHECK: __asan_report_store_n{{.*}}, i64 5)
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; CHECK: ret void
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define void @i64test_align1(i64* %b) nounwind uwtable sanitize_address {
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entry:
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store i64 0, i64* %b, align 1
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ret void
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}
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; CHECK-LABEL: i64test_align1
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; CHECK: __asan_report_store_n{{.*}}, i64 8)
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; CHECK: __asan_report_store_n{{.*}}, i64 8)
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; CHECK: ret void
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define void @i80test(i80* %a, i80* %b) nounwind uwtable sanitize_address {
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entry:
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%t = load i80* %a
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@ -20,10 +20,10 @@ entry:
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; CHECK-CUSTOM-PREFIX: call void @__foo_load8
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; CHECK-CUSTOM-PREFIX: call void @__foo_loadN
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; CHECK-INLINE-NOT: call void @__asan_load
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%tmp1 = load i32* %a
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%tmp2 = load i64* %b
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%tmp3 = load i512* %c
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%tmp4 = load i80* %d
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%tmp1 = load i32* %a, align 4
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%tmp2 = load i64* %b, align 8
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%tmp3 = load i512* %c, align 32
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%tmp4 = load i80* %d, align 8
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ret void
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}
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@ -6,7 +6,7 @@ entry:
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%tmp1 = load i32* %a, align 4
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ret i32 %tmp1
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}
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; CHECK: @read_4_bytes
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; CHECK-LABEL: @read_4_bytes
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; CHECK-NOT: ret
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; CHECK: lshr {{.*}} 3
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; Check for ASAN's Offset for 64-bit (7fff8000)
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@ -19,8 +19,10 @@ entry:
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ret void
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}
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; CHECK: @example_atomicrmw
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; CHECK-LABEL: @example_atomicrmw
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; CHECK: lshr {{.*}} 3
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; CHECK: __asan_report_store8
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; CHECK-NOT: __asan_report
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; CHECK: atomicrmw
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; CHECK: ret
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@ -30,7 +32,9 @@ entry:
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ret void
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}
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; CHECK: @example_cmpxchg
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; CHECK-LABEL: @example_cmpxchg
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; CHECK: lshr {{.*}} 3
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; CHECK: __asan_report_store8
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; CHECK-NOT: __asan_report
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; CHECK: cmpxchg
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; CHECK: ret
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