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DAGCombiner: Make the post-legalize vector op optimization more aggressive.
A legal BUILD_VECTOR goes in and gets constant folded into another legal BUILD_VECTOR so we don't lose any legality here. The problematic PPC optimization that made this check necessary was fixed recently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175759 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9262,11 +9262,6 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
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/// SimplifyVBinOp - Visit a binary vector operation, like ADD.
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SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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// After legalize, the target may be depending on adds and other
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// binary ops to provide legal ways to construct constants or other
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// things. Simplifying them may result in a loss of legality.
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if (LegalOperations) return SDValue();
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assert(N->getValueType(0).isVector() &&
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"SimplifyVBinOp only works on vectors!");
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@ -9336,11 +9331,6 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
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SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
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// After legalize, the target may be depending on adds and other
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// binary ops to provide legal ways to construct constants or other
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// things. Simplifying them may result in a loss of legality.
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if (LegalOperations) return SDValue();
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assert(N->getValueType(0).isVector() &&
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"SimplifyVUnaryOp only works on vectors!");
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@ -29,7 +29,6 @@ define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK: vsel_i64
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; CHECK: andnps
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; CHECK: andps
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; CHECK: orps
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; CHECK: ret
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@ -44,7 +43,6 @@ define void@vsel_i64(<2 x i64>* %v1, <2 x i64>* %v2) {
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK: vsel_double
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; CHECK: andnps
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; CHECK: andps
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; CHECK: orps
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; CHECK: ret
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