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Cache SelectionDAGISel TargetInstrInfo lookups on the class and
propagate. Also use the TargetSubtargetInfo and the MachineFunction and move TargetRegisterInfo query closer to uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219273 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -51,6 +51,8 @@ public:
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AliasAnalysis *AA;
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GCFunctionInfo *GFI;
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CodeGenOpt::Level OptLevel;
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const TargetInstrInfo *TII;
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static char ID;
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explicit SelectionDAGISel(TargetMachine &tm,
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@ -285,7 +285,7 @@ namespace llvm {
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ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel) {
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const TargetLowering *TLI = IS->getTargetLowering();
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const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
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const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
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if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
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TLI->getSchedulingPreference() == Sched::Source)
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@ -425,9 +425,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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NewOptLevel = CodeGenOpt::None;
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OptLevelChanger OLC(*this, NewOptLevel);
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const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getSubtargetImpl()->getRegisterInfo();
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TII = TM.getSubtargetImpl()->getInstrInfo();
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RegInfo = &MF->getRegInfo();
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AA = &getAnalysis<AliasAnalysis>();
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LibInfo = &getAnalysis<TargetLibraryInfo>();
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@ -455,7 +453,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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// copied into vregs, emit the copies into the top of the block before
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// emitting the code for the block.
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MachineBasicBlock *EntryMBB = MF->begin();
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RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
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const TargetRegisterInfo &TRI = *TM.getSubtargetImpl()->getRegisterInfo();
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RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
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DenseMap<unsigned, unsigned> LiveInMap;
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if (!FuncInfo->ArgDbgValues.empty())
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@ -496,7 +495,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
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// Def is never a terminator here, so it is ok to increment InsertPos.
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BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
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TII.get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
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TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
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Variable, Expr);
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// If this vreg is directly copied into an exported register then
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@ -517,7 +516,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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if (CopyUseMI) {
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MachineInstr *NewMI =
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BuildMI(*MF, CopyUseMI->getDebugLoc(),
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TII.get(TargetOpcode::DBG_VALUE), IsIndirect,
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TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
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CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
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MachineBasicBlock::iterator Pos = CopyUseMI;
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EntryMBB->insertAfter(Pos, NewMI);
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@ -532,8 +531,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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break;
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for (const auto &MI : MBB) {
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const MCInstrDesc &MCID =
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TM.getSubtargetImpl()->getInstrInfo()->get(MI.getOpcode());
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const MCInstrDesc &MCID = TII->get(MI.getOpcode());
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if ((MCID.isCall() && !MCID.isReturn()) ||
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MI.isStackAligningInlineAsm()) {
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MFI->setHasCalls(true);
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@ -900,8 +898,7 @@ void SelectionDAGISel::PrepareEHLandingPad() {
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// Assign the call site to the landing pad's begin label.
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MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
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const MCInstrDesc &II =
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TM.getSubtargetImpl()->getInstrInfo()->get(TargetOpcode::EH_LABEL);
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const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
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BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
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.addSym(Label);
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@ -3118,8 +3115,7 @@ SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
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if (EmitNodeInfo & OPFL_MemRefs) {
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// Only attach load or store memory operands if the generated
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// instruction may load or store.
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const MCInstrDesc &MCID =
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TM.getSubtargetImpl()->getInstrInfo()->get(TargetOpc);
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const MCInstrDesc &MCID = TII->get(TargetOpc);
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bool mayLoad = MCID.mayLoad();
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bool mayStore = MCID.mayStore();
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