6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-08 19:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Add new function UltraSparcInstrInfo::CreateZeroExtensionInstructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3581 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
2002-09-05 18:34:31 +00:00
parent 84c0fcbde4
commit f36f06bb60
1 changed files with 17 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/SparcV9/SparcV9Internals.h
View File

@@ -172,11 +172,27 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
// Create instruction sequence to produce a sign-extended register value // Create instruction sequence to produce a sign-extended register value
// from an arbitrary sized value (sized in bits, not bytes). // from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff. // Any stack space required is allocated via mcff.
// //
virtual void CreateSignExtensionInstructions(const TargetMachine& target, virtual void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F, Function* F,
Value* unsignedSrcVal, Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const;
// Create instruction sequence to produce a zero-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits, unsigned int srcSizeInBits,
Value* dest, Value* dest,
std::vector<MachineInstr*>& mvec, std::vector<MachineInstr*>& mvec,