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[SystemZ] Add a definition of the IPM instruction

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188161 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
2013-08-12 10:05:58 +00:00
parent 8d8bdff6d7
commit f37c8feb46
5 changed files with 25 additions and 4 deletions
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6
lib/Target/SystemZ/SystemZInstrFP.td
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@@ -27,9 +27,9 @@ defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
// Load zero. // Load zero.
let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LZER : InherentRRE<"lze", 0xB374, FP32, (fpimm0)>; def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
def LZDR : InherentRRE<"lzd", 0xB375, FP64, (fpimm0)>; def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
def LZXR : InherentRRE<"lzx", 0xB376, FP128, (fpimm0)>; def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
} }
// Moves between two floating-point registers. // Moves between two floating-point registers.

2
lib/Target/SystemZ/SystemZInstrFormats.td
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@@ -552,7 +552,7 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
dag src> dag src>
: InstRRE<opcode, (outs cls:$R1), (ins), : InstRRE<opcode, (outs cls:$R1), (ins),
mnemonic#"r\t$R1", mnemonic#"\t$R1",
[(set cls:$R1, src)]> { [(set cls:$R1, src)]> {
let R2 = 0; let R2 = 0;
} }

4
lib/Target/SystemZ/SystemZInstrInfo.td
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@@ -1119,6 +1119,10 @@ let Defs = [CC] in {
// Miscellaneous Instructions. // Miscellaneous Instructions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Extract CC into bits 29 and 28 of a register.
let Uses = [CC] in
def IPM : InherentRRE<"ipm", 0xB222, GR32, (null_frag)>;
// Read a 32-bit access register into a GR32. As with all GR32 operations, // Read a 32-bit access register into a GR32. As with all GR32 operations,
// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
// when a 64-bit address is stored in a pair of access registers. // when a 64-bit address is stored in a pair of access registers.

9
test/MC/Disassembler/SystemZ/insns.txt
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@@ -2260,6 +2260,15 @@
# CHECK: iill %r15, 0 # CHECK: iill %r15, 0
0xa5 0xf3 0x00 0x00 0xa5 0xf3 0x00 0x00
# CHECK: ipm %r0
0xb2 0x22 0x00 0x00
# CHECK: ipm %r1
0xb2 0x22 0x00 0x10
# CHECK: ipm %r15
0xb2 0x22 0x00 0xf0
# CHECK: la %r0, 0 # CHECK: la %r0, 0
0x41 0x00 0x00 0x00 0x41 0x00 0x00 0x00

8
test/MC/SystemZ/insn-good.s
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@@ -3593,6 +3593,14 @@
iill %r0, 0xffff iill %r0, 0xffff
iill %r15, 0 iill %r15, 0
#CHECK: ipm %r0 # encoding: [0xb2,0x22,0x00,0x00]
#CHECK: ipm %r1 # encoding: [0xb2,0x22,0x00,0x10]
#CHECK: ipm %r15 # encoding: [0xb2,0x22,0x00,0xf0]
ipm %r0
ipm %r1
ipm %r15
#CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00] #CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00]
#CHECK: l %r0, 4095 # encoding: [0x58,0x00,0x0f,0xff] #CHECK: l %r0, 4095 # encoding: [0x58,0x00,0x0f,0xff]
#CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00] #CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00]