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add a "load effective address"

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-08-17 17:09:40 +00:00
parent d337295fb0
commit f3a335cedf
5 changed files with 48 additions and 10 deletions
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24
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -59,19 +59,27 @@ namespace {
return "ARM Assembly Printer";
}
void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO1 = MI->getOperand(OpNo);
const MachineOperand &MO2 = MI->getOperand(OpNo + 1);
void printMemRegImm(const MachineInstr *MI, int opNum,
const char *Modifier = NULL) {
const MachineOperand &MO1 = MI->getOperand(opNum);
const MachineOperand &MO2 = MI->getOperand(opNum + 1);
assert(MO1.isImmediate());
bool arith = false;
if (Modifier != NULL) {
assert(strcmp(Modifier, "arith") == 0);
arith = true;
}
if (MO2.isConstantPoolIndex()) {
printOperand(MI, OpNo + 1);
printOperand(MI, opNum + 1);
} else if (MO2.isRegister()) {
O << '[';
printOperand(MI, OpNo + 1);
if(!arith)
O << '[';
printOperand(MI, opNum + 1);
O << ", ";
printOperand(MI, OpNo);
O << ']';
printOperand(MI, opNum);
if(!arith)
O << ']';
} else {
assert(0 && "Invalid Operand Type");
}

5
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -358,6 +358,11 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
//register plus/minus 12 bit offset
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
SDOperand &Base) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isInt12Immediate(N.getOperand(1), imm)) {

8
lib/Target/ARM/ARMInstrInfo.td
View File

@ -21,7 +21,7 @@ def memri : Operand<iPTR> {
// Define ARM specific addressing mode.
//register plus/minus 12 bit offset
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", []>;
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
//register plus scaled register
//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
@ -83,6 +83,12 @@ def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
"add $dst, $a, $b",
[(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
"add $dst, ${addr:arith}",
[(set IntRegs:$dst, iaddr:$addr)]>;
def subri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
"sub $dst, $a, $b",
[(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;

3
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -89,7 +89,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineFunction &MF = *MBB.getParent();
assert (MI.getOpcode() == ARM::ldr ||
MI.getOpcode() == ARM::str);
MI.getOpcode() == ARM::str ||
MI.getOpcode() == ARM::lea_addri);
unsigned FrameIdx = 2;
unsigned OffIdx = 1;

18
test/CodeGen/ARM/argaddr.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llvm-as < %s | llc -march=arm
void %f(int %a, int %b, int %c, int %d, int %e) {
entry:
%a_addr = alloca int ; <int*> [#uses=2]
%b_addr = alloca int ; <int*> [#uses=2]
%c_addr = alloca int ; <int*> [#uses=2]
%d_addr = alloca int ; <int*> [#uses=2]
%e_addr = alloca int ; <int*> [#uses=2]
store int %a, int* %a_addr
store int %b, int* %b_addr
store int %c, int* %c_addr
store int %d, int* %d_addr
store int %e, int* %e_addr
call void %g( int* %a_addr, int* %b_addr, int* %c_addr, int* %d_addr, int* %e_addr )
ret void
}
declare void %g(int*, int*, int*, int*, int*)