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[mips][mips64r6] Add BLTC and BLTUC instructions

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Differential Revision: http://reviews.llvm.org/D3923


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
2014-06-18 14:36:00 +00:00
parent 7047ad9a08
commit f3a4a4bb56
6 changed files with 33 additions and 6 deletions
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19
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@@ -576,6 +576,8 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
// BLTZC if rs == rt && rt != 0
// BLTC if rs != rt && rs != 0 && rt != 0
bool HasRs = false;
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
@@ -586,8 +588,14 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
MI.setOpcode(Mips::BGTZC);
else if (Rs == Rt)
MI.setOpcode(Mips::BLTZC);
else
return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
else {
MI.setOpcode(Mips::BLTC);
HasRs = true;
}
if (HasRs)
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
@@ -627,8 +635,11 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
} else if (Rs == Rt) {
MI.setOpcode(Mips::BLTZALC);
HasRs = true;
} else
return MCDisassembler::Fail; // BLTUC not implemented yet
} else {
MI.setOpcode(Mips::BLTUC);
HasRs = true;
HasRt = true;
}
if (HasRs)
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,