From f3ba434781daa1c2b16f77a91e5209c21ce12428 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 8 Mar 2008 23:43:36 +0000 Subject: [PATCH] Teach SD some vector identities, allowing us to compile vec_set-9 into: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48058 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 14 +++++++++++++- test/CodeGen/X86/vec_set-9.ll | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/vec_set-9.ll diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index b3251b066a4..f81d80ebe79 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1889,6 +1889,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) && MVT::getVectorElementType(VT) == Operand.getValueType() && "Illegal SCALAR_TO_VECTOR node!"); + if (OpOpcode == ISD::UNDEF) + return getNode(ISD::UNDEF, VT); + // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. + if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && + isa(Operand.getOperand(1)) && + Operand.getConstantOperandVal(1) == 0 && + Operand.getOperand(0).getValueType() == VT) + return Operand.getOperand(0); break; case ISD::FNEG: if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) @@ -2039,6 +2047,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, case ISD::EXTRACT_VECTOR_ELT: assert(N2C && "Bad EXTRACT_VECTOR_ELT!"); + // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. + if (N1.getOpcode() == ISD::UNDEF) + return getNode(ISD::UNDEF, VT); + // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is // expanding copies of large vectors from registers. if (N1.getOpcode() == ISD::CONCAT_VECTORS && @@ -2054,7 +2066,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, // expanding large vector constants. if (N1.getOpcode() == ISD::BUILD_VECTOR) return N1.getOperand(N2C->getValue()); - + // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector // operations are lowered to scalars. if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) diff --git a/test/CodeGen/X86/vec_set-9.ll b/test/CodeGen/X86/vec_set-9.ll new file mode 100644 index 00000000000..d00ceff5404 --- /dev/null +++ b/test/CodeGen/X86/vec_set-9.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 1 + +define <2 x i64> @test3(i64 %A) { +entry: + %B = insertelement <2 x i64> undef, i64 %A, i32 1 + ret <2 x i64> %B +} +