diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index d7e92db89df..bb6b7672b8a 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -20,6 +20,7 @@ def it_pred : Operand<i32> {
 // IT block condition mask
 def it_mask : Operand<i32> {
   let PrintMethod = "printThumbITMask";
+  let DecoderMethod = "DecodeITMask";
 }
 
 // Shifted operands. No register controlled shifts for Thumb2.
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index e22126956e7..83a8f800608 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -230,6 +230,8 @@ static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
+                                uint64_t Address, const void *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 #include "ARMGenInstrInfo.inc"
@@ -3304,3 +3306,14 @@ static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
   return S;
 }
 
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
+                                 uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+  if (Mask == 0) {
+    Mask = 0x8;
+    CHECK(S, Unpredictable);
+  }
+  Inst.addOperand(MCOperand::CreateImm(Mask));
+  return S;
+}
+