6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-04 22:07:27 +00:00
Code Issues Projects Releases Wiki Activity

MFTB on PPC64 should really be encoded using MFSPR.

Browse Source 
The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.

Thanks to Adhemerval Zanella for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2012-08-06 21:21:44 +00:00
parent b0f6759ab9
commit f45717e985
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -266,8 +266,8 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
}
let Pattern = [(set G8RC:$rT, readcyclecounter)] in
def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
"mftb $rT", SprMFTB>,
def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
"mfspr $rT, 268", SprMFTB>,
PPC970_DGroup_First, PPC970_Unit_FXU;
let Defs = [X1], Uses = [X1] in

2
test/CodeGen/PowerPC/ppc64-cyclecounter.ll
View File

@ -9,7 +9,7 @@ entry:
}
; CHECK: @test1
; CHECK: mftb
; CHECK: mfspr 3, 268
declare i64 @llvm.readcyclecounter()