6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Fix emergency spilling in LiveIntervals::spillPhysRegAroundRegDefsUses.

Browse Source 
Always spill the full representative register at any point where any subregister
is live.

This fixes PR8620 which caused the old logic to get confused and not spill
anything at all.

The fundamental problem here is that the coalescer is too aggressive about
physical register coalescing. It sometimes makes it impossible to allocate
registers without these emergency spills.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119375 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-11-16 19:55:14 +00:00
parent fd900a2c07
commit f4840c07f8
1 changed files with 23 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -1928,6 +1928,9 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
unsigned PhysReg, VirtRegMap &vrm) {
unsigned SpillReg = getRepresentativeReg(PhysReg);
DEBUG(dbgs() << "spillPhysRegAroundRegDefsUses " << tri_->getName(PhysReg)
<< " represented by " << tri_->getName(SpillReg) << '\n');
for (const unsigned *AS = tri_->getAliasSet(PhysReg); *AS; ++AS)
// If there are registers which alias PhysReg, but which are not a
// sub-register of the chosen representative super register. Assert
@ -1939,15 +1942,16 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
SmallVector<unsigned, 4> PRegs;
if (hasInterval(SpillReg))
PRegs.push_back(SpillReg);
else {
SmallSet<unsigned, 4> Added;
for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS)
if (Added.insert(*AS) && hasInterval(*AS)) {
PRegs.push_back(*AS);
for (const unsigned* ASS = tri_->getSubRegisters(*AS); *ASS; ++ASS)
Added.insert(*ASS);
}
}
for (const unsigned *SR = tri_->getSubRegisters(SpillReg); *SR; ++SR)
if (hasInterval(*SR))
PRegs.push_back(*SR);
DEBUG({
dbgs() << "Trying to spill:";
for (unsigned i = 0, e = PRegs.size(); i != e; ++i)
dbgs() << ' ' << tri_->getName(PRegs[i]);
dbgs() << '\n';
});
SmallPtrSet<MachineInstr*, 8> SeenMIs;
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg),
@ -1958,18 +1962,16 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
continue;
SeenMIs.insert(MI);
SlotIndex Index = getInstructionIndex(MI);
bool LiveReg = false;
for (unsigned i = 0, e = PRegs.size(); i != e; ++i) {
unsigned PReg = PRegs[i];
LiveInterval &pli = getInterval(PReg);
if (!pli.liveAt(Index))
continue;
vrm.addEmergencySpill(PReg, MI);
LiveReg = true;
SlotIndex StartIdx = Index.getLoadIndex();
SlotIndex EndIdx = Index.getNextIndex().getBaseIndex();
if (pli.isInOneLiveRange(StartIdx, EndIdx)) {
pli.removeRange(StartIdx, EndIdx);
Cut = true;
} else {
if (!pli.isInOneLiveRange(StartIdx, EndIdx)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Ran out of registers during register allocation!";
@ -1980,15 +1982,14 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
}
report_fatal_error(Msg.str());
}
for (const unsigned* AS = tri_->getSubRegisters(PReg); *AS; ++AS) {
if (!hasInterval(*AS))
continue;
LiveInterval &spli = getInterval(*AS);
if (spli.liveAt(Index))
spli.removeRange(Index.getLoadIndex(),
Index.getNextIndex().getBaseIndex());
}
pli.removeRange(StartIdx, EndIdx);
LiveReg = true;
}
if (!LiveReg)
continue;
DEBUG(dbgs() << "Emergency spill around " << Index << '\t' << *MI);
vrm.addEmergencySpill(SpillReg, MI);
Cut = true;
}
return Cut;
}