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Copy the liveins for the first block. PR859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29511 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14,9 +14,11 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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@ -669,6 +671,18 @@ void ScheduleDAGSimple::dump() const {
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/// EmitAll - Emit all nodes in schedule sorted order.
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/// EmitAll - Emit all nodes in schedule sorted order.
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///
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///
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void ScheduleDAGSimple::EmitAll() {
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void ScheduleDAGSimple::EmitAll() {
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// If this is the first basic block in the function, and if it has live ins
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// that need to be copied into vregs, emit the copies into the top of the
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// block before emitting the code for the block.
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MachineFunction &MF = DAG.getMachineFunction();
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if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
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for (MachineFunction::livein_iterator LI = MF.livein_begin(),
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E = MF.livein_end(); LI != E; ++LI)
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if (LI->second)
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MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
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LI->first, RegMap->getRegClass(LI->second));
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}
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std::map<SDNode*, unsigned> VRBaseMap;
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std::map<SDNode*, unsigned> VRBaseMap;
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// For each node in the ordering
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// For each node in the ordering
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