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Copy the liveins for the first block. PR859

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2006-08-03 20:51:06 +00:00
parent 93d537c1d6
commit f492391de0
1 changed files with 14 additions and 0 deletions
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14
lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
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@ -14,9 +14,11 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -669,6 +671,18 @@ void ScheduleDAGSimple::dump() const {
/// EmitAll - Emit all nodes in schedule sorted order.
///
void ScheduleDAGSimple::EmitAll() {
// If this is the first basic block in the function, and if it has live ins
// that need to be copied into vregs, emit the copies into the top of the
// block before emitting the code for the block.
MachineFunction &MF = DAG.getMachineFunction();
if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
E = MF.livein_end(); LI != E; ++LI)
if (LI->second)
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
LI->first, RegMap->getRegClass(LI->second));
}
std::map<SDNode*, unsigned> VRBaseMap;
// For each node in the ordering