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Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>

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My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used.  This
caused massive failures on the testsuite when compiling for Thumb1.  While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-12-22 23:39:48 +00:00
parent bfbc9fcb83
commit f4aea8f349
4 changed files with 23 additions and 7 deletions
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4
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -842,7 +842,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.eraseFromParent();
return true;
}
case ARM::eh_sjlj_dispatchsetup: {
case ARM::Int_eh_sjlj_dispatchsetup:
case ARM::Int_eh_sjlj_dispatchsetup_nofp:
case ARM::tInt_eh_sjlj_dispatchsetup: {
MachineFunction &MF = *MI.getParent()->getParent();
const ARMBaseInstrInfo *AII =
static_cast<const ARMBaseInstrInfo*>(TII);

7
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5792,7 +5792,12 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
MachineMemOperand::MOLoad |
MachineMemOperand::MOVolatile, 4, 4);
BuildMI(DispatchBB, dl, TII->get(ARM::eh_sjlj_dispatchsetup));
if (AFI->isThumb1OnlyFunction())
BuildMI(DispatchBB, dl, TII->get(ARM::tInt_eh_sjlj_dispatchsetup));
else if (!Subtarget->hasVFP2())
BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup_nofp));
else
BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
unsigned NumLPads = LPadList.size();
if (Subtarget->isThumb2()) {

15
lib/Target/ARM/ARMInstrInfo.td
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@ -4737,15 +4737,20 @@ def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
Requires<[IsARM, IsIOS]>;
}
// eh.sjlj.dispatchsetup pseudo-instruction.
// This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
// eh.sjlj.dispatchsetup pseudo-instructions.
// These pseudos are used for both ARM and Thumb2. Any differences are
// handled when the pseudo is expanded (which happens before any passes
// that need the instruction size).
let Defs =
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], isBarrier = 1 in {
def eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
}
QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], isBarrier = 1 in
def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
let Defs =
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
isBarrier = 1 in
def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns

4
lib/Target/ARM/ARMInstrThumb.td
View File

@ -1271,6 +1271,10 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
[(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
Requires<[IsThumb, IsIOS]>;
let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
isBarrier = 1 in
def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//