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Add support for .cfi_register now that it is easy to extent the representation
to support it. Original patch with the parsing and plumbing by the PaX team and Roman Divacky. I added the bits in MCDwarf.cpp and the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168565 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -267,18 +267,27 @@ namespace llvm {
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public:
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enum OpType { OpSameValue, OpRememberState, OpRestoreState, OpOffset,
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OpDefCfaRegister, OpDefCfaOffset, OpDefCfa, OpRelOffset,
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OpAdjustCfaOffset, OpEscape, OpRestore, OpUndefined };
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OpAdjustCfaOffset, OpEscape, OpRestore, OpUndefined,
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OpRegister };
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private:
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OpType Operation;
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MCSymbol *Label;
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unsigned Register;
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int Offset;
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union {
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int Offset;
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unsigned Register2;
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};
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std::vector<char> Values;
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MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R,
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int O, StringRef V) :
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MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V) :
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Operation(Op), Label(L), Register(R), Offset(O),
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Values(V.begin(), V.end()) {
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assert(Op != OpRegister);
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}
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MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R1, unsigned R2) :
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Operation(Op), Label(L), Register(R1), Register2(R2) {
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assert(Op == OpRegister);
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}
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public:
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@ -335,6 +344,11 @@ namespace llvm {
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return MCCFIInstruction(OpEscape, L, 0, 0, Vals);
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}
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static MCCFIInstruction
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createRegister(MCSymbol *L, unsigned Register1, unsigned Register2) {
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return MCCFIInstruction(OpRegister, L, Register1, Register2);
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}
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OpType getOperation() const { return Operation; }
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MCSymbol *getLabel() const { return Label; }
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@ -342,10 +356,15 @@ namespace llvm {
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assert(Operation == OpDefCfa || Operation == OpOffset ||
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Operation == OpRestore || Operation == OpUndefined ||
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Operation == OpSameValue || Operation == OpDefCfaRegister ||
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Operation == OpRelOffset);
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Operation == OpRelOffset || Operation == OpRegister);
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return Register;
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}
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unsigned getRegister2() const {
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assert(Operation == OpRegister);
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return Register2;
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}
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int getOffset() const {
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assert(Operation == OpDefCfa || Operation == OpOffset ||
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Operation == OpRelOffset || Operation == OpDefCfaOffset ||
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@ -517,6 +517,7 @@ namespace llvm {
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virtual void EmitCFIEscape(StringRef Values);
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virtual void EmitCFISignalFrame();
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virtual void EmitCFIUndefined(int64_t Register);
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virtual void EmitCFIRegister(int64_t Register1, int64_t Register2);
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virtual void EmitWin64EHStartProc(const MCSymbol *Symbol);
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virtual void EmitWin64EHEndProc();
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@ -227,6 +227,7 @@ public:
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virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment);
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virtual void EmitCFISignalFrame();
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virtual void EmitCFIUndefined(int64_t Register);
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virtual void EmitCFIRegister(int64_t Register1, int64_t Register2);
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virtual void EmitWin64EHStartProc(const MCSymbol *Symbol);
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virtual void EmitWin64EHEndProc();
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@ -1047,6 +1048,16 @@ void MCAsmStreamer::EmitCFIUndefined(int64_t Register) {
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EmitEOL();
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}
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void MCAsmStreamer::EmitCFIRegister(int64_t Register1, int64_t Register2) {
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MCStreamer::EmitCFIRegister(Register1, Register2);
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if (!UseCFI)
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return;
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OS << "\t.cfi_register " << Register1 << ", " << Register2;
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EmitEOL();
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}
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void MCAsmStreamer::EmitWin64EHStartProc(const MCSymbol *Symbol) {
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MCStreamer::EmitWin64EHStartProc(Symbol);
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@ -938,6 +938,19 @@ void FrameEmitterImpl::EmitCFIInstruction(MCStreamer &Streamer,
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bool VerboseAsm = Streamer.isVerboseAsm();
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switch (Instr.getOperation()) {
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case MCCFIInstruction::OpRegister: {
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unsigned Reg1 = Instr.getRegister();
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unsigned Reg2 = Instr.getRegister2();
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if (VerboseAsm) {
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Streamer.AddComment("DW_CFA_register");
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Streamer.AddComment(Twine("Reg1 ") + Twine(Reg1));
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Streamer.AddComment(Twine("Reg2 ") + Twine(Reg2));
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}
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Streamer.EmitIntValue(dwarf::DW_CFA_register, 1);
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Streamer.EmitULEB128IntValue(Reg1);
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Streamer.EmitULEB128IntValue(Reg2);
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return;
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}
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case MCCFIInstruction::OpUndefined: {
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unsigned Reg = Instr.getRegister();
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if (VerboseAsm) {
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@ -398,6 +398,8 @@ public:
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&GenericAsmParser::ParseDirectiveCFISignalFrame>(".cfi_signal_frame");
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AddDirectiveHandler<
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&GenericAsmParser::ParseDirectiveCFIUndefined>(".cfi_undefined");
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AddDirectiveHandler<
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&GenericAsmParser::ParseDirectiveCFIRegister>(".cfi_register");
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// Macro directives.
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AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacrosOnOff>(
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@ -436,6 +438,7 @@ public:
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bool ParseDirectiveCFIEscape(StringRef, SMLoc DirectiveLoc);
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bool ParseDirectiveCFISignalFrame(StringRef, SMLoc DirectiveLoc);
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bool ParseDirectiveCFIUndefined(StringRef, SMLoc DirectiveLoc);
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bool ParseDirectiveCFIRegister(StringRef, SMLoc DirectiveLoc);
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bool ParseDirectiveMacrosOnOff(StringRef, SMLoc DirectiveLoc);
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bool ParseDirectiveMacro(StringRef, SMLoc DirectiveLoc);
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@ -3263,6 +3266,29 @@ bool GenericAsmParser::ParseDirectiveCFIUndefined(StringRef Directive,
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return false;
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}
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/// ParseDirectiveCFIRegister
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/// ::= .cfi_register register, register
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bool GenericAsmParser::ParseDirectiveCFIRegister(StringRef Directive,
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SMLoc DirectiveLoc) {
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int64_t Register1 = 0;
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if (ParseRegisterOrRegisterNumber(Register1, DirectiveLoc))
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return true;
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if (getLexer().isNot(AsmToken::Comma))
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return TokError("unexpected token in directive");
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Lex();
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int64_t Register2 = 0;
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if (ParseRegisterOrRegisterNumber(Register2, DirectiveLoc))
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return true;
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getStreamer().EmitCFIRegister(Register1, Register2);
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return false;
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}
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/// ParseDirectiveMacrosOnOff
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/// ::= .macros_on
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/// ::= .macros_off
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@ -356,6 +356,14 @@ void MCStreamer::EmitCFIUndefined(int64_t Register) {
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CurFrame->Instructions.push_back(Instruction);
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}
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void MCStreamer::EmitCFIRegister(int64_t Register1, int64_t Register2) {
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MCSymbol *Label = EmitCFICommon();
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MCCFIInstruction Instruction =
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MCCFIInstruction::createRegister(Label, Register1, Register2);
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MCDwarfFrameInfo *CurFrame = getCurrentFrameInfo();
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CurFrame->Instructions.push_back(Instruction);
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}
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void MCStreamer::setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame) {
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W64UnwindInfos.push_back(Frame);
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CurrentW64UnwindInfo = W64UnwindInfos.back();
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42
test/MC/ELF/cfi-register.s
Normal file
42
test/MC/ELF/cfi-register.s
Normal file
@ -0,0 +1,42 @@
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// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s
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f:
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.cfi_startproc
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nop
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.cfi_register %rbp, %rax
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nop
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.cfi_endproc
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// CHECK: # Section 4
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// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame'
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// CHECK-NEXT: ('sh_type', 0x00000001)
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// CHECK-NEXT: ('sh_flags', 0x0000000000000002)
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// CHECK-NEXT: ('sh_addr', 0x0000000000000000)
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// CHECK-NEXT: ('sh_offset', 0x0000000000000048)
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// CHECK-NEXT: ('sh_size', 0x0000000000000030)
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// CHECK-NEXT: ('sh_link', 0x00000000)
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// CHECK-NEXT: ('sh_info', 0x00000000)
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// CHECK-NEXT: ('sh_addralign', 0x0000000000000008)
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// CHECK-NEXT: ('sh_entsize', 0x0000000000000000)
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// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410906 00000000')
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// CHECK-NEXT: ),
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// CHECK-NEXT: # Section 5
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// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame'
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// CHECK-NEXT: ('sh_type', 0x00000004)
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// CHECK-NEXT: ('sh_flags', 0x0000000000000000)
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// CHECK-NEXT: ('sh_addr', 0x0000000000000000)
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// CHECK-NEXT: ('sh_offset', 0x0000000000000390)
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// CHECK-NEXT: ('sh_size', 0x0000000000000018)
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// CHECK-NEXT: ('sh_link', 0x00000007)
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// CHECK-NEXT: ('sh_info', 0x00000004)
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// CHECK-NEXT: ('sh_addralign', 0x0000000000000008)
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// CHECK-NEXT: ('sh_entsize', 0x0000000000000018)
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// CHECK-NEXT: ('_relocations', [
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// CHECK-NEXT: # Relocation 0
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// CHECK-NEXT: (('r_offset', 0x0000000000000020)
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// CHECK-NEXT: ('r_sym', 0x00000002)
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// CHECK-NEXT: ('r_type', 0x00000002)
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// CHECK-NEXT: ('r_addend', 0x0000000000000000)
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// CHECK-NEXT: ),
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// CHECK-NEXT: ])
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// CHECK-NEXT: ),
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