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ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
f39031b360
commit
f4fa3d6e46
@ -665,11 +665,17 @@ def addrmode2 : Operand<i32>,
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def PostIdxRegShiftedAsmOperand : AsmOperandClass {
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let Name = "PostIdxRegShifted";
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let ParserMethod = "parsePostIdxReg";
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}
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def am2offset_reg : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
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[], [SDNPWantRoot]> {
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let EncoderMethod = "getAddrMode2OffsetOpValue";
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let PrintMethod = "printAddrMode2OffsetOperand";
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// When using this for assembly, it's always as a post-index offset.
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let ParserMatchClass = PostIdxRegShiftedAsmOperand;
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let MIOperandInfo = (ops GPR, i32imm);
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}
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@ -232,7 +232,9 @@ class ARMOperand : public MCParsedAsmOperand {
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struct {
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unsigned RegNum;
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unsigned Imm;
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bool isAdd;
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ARM_AM::ShiftOpc ShiftTy;
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unsigned ShiftImm;
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} PostIdxReg;
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struct {
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@ -498,12 +500,15 @@ public:
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bool isToken() const { return Kind == Token; }
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bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
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bool isMemory() const { return Kind == Memory; }
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bool isPostIdxReg() const { return Kind == PostIndexRegister; }
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bool isShifterImm() const { return Kind == ShifterImmediate; }
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bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
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bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
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bool isRotImm() const { return Kind == RotateImmediate; }
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bool isBitfield() const { return Kind == BitfieldDescriptor; }
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bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
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bool isPostIdxReg() const {
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return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
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}
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bool isMemNoOffset() const {
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if (Kind != Memory)
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return false;
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@ -858,7 +863,18 @@ public:
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void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
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Inst.addOperand(MCOperand::CreateImm(PostIdxReg.Imm));
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Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
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}
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void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
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// The sign, shift type, and shift amount are encoded in a single operand
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// using the AM2 encoding helpers.
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ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
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unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
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PostIdxReg.ShiftTy);
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Inst.addOperand(MCOperand::CreateImm(Imm));
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}
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void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
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@ -1027,11 +1043,15 @@ public:
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return Op;
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}
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static ARMOperand *CreatePostIdxReg(unsigned RegNum, unsigned Imm,
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static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
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ARM_AM::ShiftOpc ShiftTy,
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unsigned ShiftImm,
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SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(PostIndexRegister);
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Op->PostIdxReg.RegNum = RegNum;
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Op->PostIdxReg.Imm = Imm;
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Op->PostIdxReg.isAdd = isAdd;
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Op->PostIdxReg.ShiftTy = ShiftTy;
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Op->PostIdxReg.ShiftImm = ShiftImm;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -1093,9 +1113,12 @@ void ARMOperand::print(raw_ostream &OS) const {
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OS << ">";
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break;
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case PostIndexRegister:
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OS << "post-idx register " << (PostIdxReg.Imm ? "" : "-")
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<< PostIdxReg.RegNum
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<< ">";
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OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
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<< PostIdxReg.RegNum;
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if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
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OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
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<< PostIdxReg.ShiftImm;
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OS << ">";
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break;
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case ProcIFlags: {
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OS << "<ARM_PROC::";
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@ -1861,9 +1884,9 @@ parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Check for a post-index addressing register operand. Specifically:
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// postidx_reg := '+' register
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// | '-' register
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// | register
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// postidx_reg := '+' register {, shift}
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// | '-' register {, shift}
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// | register {, shift}
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// This method must return MatchOperand_NoMatch without consuming any tokens
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// in the case where there is no match, as other alternatives take other
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@ -1891,7 +1914,11 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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}
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SMLoc E = Parser.getTok().getLoc();
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Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, S, E));
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ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
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unsigned ShiftImm = 0;
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Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
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ShiftImm, S, E));
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return MatchOperand_Success;
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}
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@ -2107,7 +2134,12 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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ShiftType, ShiftValue, isNegative,
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S, E));
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// If there's a pre-indexing writeback marker, '!', just add it as a token
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// operand.
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if (Parser.getTok().is(AsmToken::Exclaim)) {
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Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
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Parser.Lex(); // Eat the '!'.
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}
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return false;
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}
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@ -24,3 +24,19 @@ _func:
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@ CHECK: ldr r3, [r1], #-30 @ encoding: [0x1e,0x30,0x11,0xe4]
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@------------------------------------------------------------------------------
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@ LDR (register)
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@------------------------------------------------------------------------------
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ldr r3, [r8, r1]
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ldr r2, [r5, -r3]
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ldr r1, [r5, r9]!
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ldr r6, [r7, -r8]!
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ldr r5, [r9], r2
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ldr r4, [r3], -r6
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@ CHECK: ldr r3, [r8, r1] @ encoding: [0x01,0x30,0x98,0xe7]
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@ CHECK: ldr r2, [r5, -r3] @ encoding: [0x03,0x20,0x15,0xe7]
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@ CHECK: ldr r1, [r5, r9]! @ encoding: [0x09,0x10,0xb5,0xe7]
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@ CHECK: ldr r6, [r7, -r8]! @ encoding: [0x08,0x60,0x37,0xe7]
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@ CHECK: ldr r5, [r9], r2 @ encoding: [0x02,0x50,0x99,0xe6]
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@ CHECK: ldr r4, [r3], -r6 @ encoding: [0x06,0x40,0x13,0xe6]
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