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Simple branch relaxation for Thumb2 Bcc instructions.

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Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-12-05 23:45:46 +00:00
parent 5792051bfc
commit f503ef6800
1 changed files with 24 additions and 3 deletions
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27
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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@ -124,14 +124,35 @@ public:
};
} // end anonymous namespace
static unsigned getRelaxedOpcode(unsigned Op) {
switch (Op) {
default: return Op;
case ARM::tBcc: return ARM::t2Bcc;
}
}
bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
// FIXME: Thumb targets, different move constant targets..
if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
return true;
return false;
}
void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
return;
unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
// Sanity check w/ diagnostic if we get here w/ a bogus instruction.
if (RelaxedOp == Inst.getOpcode()) {
SmallString<256> Tmp;
raw_svector_ostream OS(Tmp);
Inst.dump_pretty(OS);
OS << "\n";
report_fatal_error("unexpected instruction to relax: " + OS.str());
}
// The instructions we're relaxing have (so far) the same operands.
// We just need to update to the proper opcode.
Res = Inst;
Res.setOpcode(RelaxedOp);
}
bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {