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[mips] First patch which adds support for micromips.
This patch adds support for recoded (meaning assembly-language compatible to standard mips32) arithmetic 32-bit instructions. Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
8d99ec5748
commit
f530aff9de
@ -27,6 +27,9 @@
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_INSTRMAP_INFO
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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namespace {
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@ -35,12 +38,13 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
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void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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const MCSubtargetInfo &STI;
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bool IsLittleEndian;
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public:
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MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
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const MCSubtargetInfo &sti, bool IsLittle) :
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MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
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MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {}
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~MipsMCCodeEmitter() {}
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@ -144,6 +148,15 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
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llvm_unreachable("unimplemented opcode in EncodeInstruction()");
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if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
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int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
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if (NewOpcode != -1) {
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Opcode = NewOpcode;
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TmpInst.setOpcode (NewOpcode);
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Binary = getBinaryCodeForInstr(TmpInst, Fixups);
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}
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}
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const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
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// Get byte count of instruction
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70
lib/Target/Mips/MicroMipsInstrFormats.td
Normal file
70
lib/Target/Mips/MicroMipsInstrFormats.td
Normal file
@ -0,0 +1,70 @@
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class MMArch {
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string Arch = "micromips";
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list<dag> Pattern = [];
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}
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class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {
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bits<5> rt;
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bits<5> rs;
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bits<5> rd;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0;
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let Inst{9-0} = funct;
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}
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class ADDI_FM_MM<bits<6> op> : MMArch {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm16;
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}
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class SLTI_FM_MM<bits<6> op> : MMArch {
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class LUI_FM_MM : MMArch {
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = 0x10;
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let Inst{25-21} = 0xd;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class MULT_FM_MM<bits<10> funct> : MMArch {
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0x00;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0x3c;
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}
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39
lib/Target/Mips/MicroMipsInstrInfo.td
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39
lib/Target/Mips/MicroMipsInstrInfo.td
Normal file
@ -0,0 +1,39 @@
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let isCodeGenOnly = 1 in {
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd>,
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ADDI_FM_MM<0xc>;
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def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>,
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ADDI_FM_MM<0x4>;
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def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
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SLTI_FM_MM<0x24>;
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
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SLTI_FM_MM<0x2c>;
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
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ADDI_FM_MM<0x34>;
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def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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ADDI_FM_MM<0x14>;
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
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ADDI_FM_MM<0x1c>;
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def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu_MM : MMRel, ArithLogicR<"addu", CPURegsOpnd>, ADD_FM_MM<0, 0x150>;
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def SUBu_MM : MMRel, ArithLogicR<"subu", CPURegsOpnd>, ADD_FM_MM<0, 0x1d0>;
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def MUL_MM : MMRel, ArithLogicR<"mul", CPURegsOpnd>, ADD_FM_MM<0, 0x210>;
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def ADD_MM : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM_MM<0, 0x110>;
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def SUB_MM : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM_MM<0, 0x190>;
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def SLT_MM : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM_MM<0, 0x350>;
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def SLTu_MM : MMRel, SetCC_R<"sltu", setult, CPURegs>,
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ADD_FM_MM<0, 0x390>;
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def AND_MM : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
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ADD_FM_MM<0, 0x250>;
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def OR_MM : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
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ADD_FM_MM<0, 0x290>;
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def XOR_MM : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
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ADD_FM_MM<0, 0x310>;
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def NOR_MM : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM_MM<0, 0x2d0>;
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def MULT_MM : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
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MULT_FM_MM<0x22c>;
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def MULTu_MM : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
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MULT_FM_MM<0x26c>;
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}
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@ -36,6 +36,24 @@ def FrmFR : Format<4>;
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def FrmFI : Format<5>;
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def FrmOther : Format<6>; // Instruction w/ a custom format
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class MMRel;
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def Std2MicroMips : InstrMapping {
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let FilterClass = "MMRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["Arch"];
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// The key column is the unpredicated instructions.
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let KeyCol = ["se"];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["se"], ["micromips"]];
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}
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class StdArch {
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string Arch = "se";
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}
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// Generic Mips Format
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class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>: Instruction
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@ -74,9 +92,11 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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// Mips32/64 Instruction Format
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class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>:
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InstrItinClass itin, Format f, string opstr = ""> :
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MipsInst<outs, ins, asmstr, pattern, itin, f> {
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let Predicates = [HasStdEnc];
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string BaseOpcode = opstr;
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string Arch;
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}
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// Mips Pseudo Instructions Format
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@ -192,7 +212,7 @@ class MFC3OP_FM<bits<6> op, bits<5> mfmt>
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let Inst{2-0} = sel;
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}
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class ADD_FM<bits<6> op, bits<6> funct> {
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class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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@ -207,7 +227,7 @@ class ADD_FM<bits<6> op, bits<6> funct> {
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let Inst{5-0} = funct;
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}
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class ADDI_FM<bits<6> op> {
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class ADDI_FM<bits<6> op> : StdArch {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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@ -288,7 +308,7 @@ class B_FM {
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let Inst{15-0} = offset;
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}
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class SLTI_FM<bits<6> op> {
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class SLTI_FM<bits<6> op> : StdArch {
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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@ -413,7 +433,7 @@ class SYNC_FM {
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let Inst{5-0} = 0xf;
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}
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class MULT_FM<bits<6> op, bits<6> funct> {
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class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
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bits<5> rs;
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bits<5> rt;
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@ -375,11 +375,9 @@ class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
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SDPatternOperator OpNode = null_frag>:
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InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
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[(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
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let isCommutable = isComm;
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let isReMaterializable = 1;
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string BaseOpcode;
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string Arch;
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}
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// Arithmetic and logical instructions with 2 register operands.
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@ -388,7 +386,8 @@ class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
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!strconcat(opstr, "\t$rt, $rs, $imm16"),
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[(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> {
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[(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
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IIAlu, FrmI, opstr> {
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let isReMaterializable = 1;
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}
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@ -405,7 +404,7 @@ class MArithR<string opstr, bit isComm = 0> :
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class LogicNOR<string opstr, RegisterOperand RC>:
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InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
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[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> {
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let isCommutable = 1;
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}
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@ -543,14 +542,15 @@ class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
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class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
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InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
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[(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
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IIAlu, FrmR, opstr>;
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class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
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RegisterClass RC>:
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InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(opstr, "\t$rt, $rs, $imm16"),
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[(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
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IIAlu, FrmI>;
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IIAlu, FrmI, opstr>;
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// Jump
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class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
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@ -637,7 +637,7 @@ class SYNC_FT :
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class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
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list<Register> DefRegs> :
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InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
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itin, FrmR> {
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itin, FrmR, opstr> {
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let isCommutable = 1;
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let Defs = DefRegs;
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let neverHasSideEffects = 1;
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@ -849,31 +849,39 @@ def COPY_AC64 : PseudoSE<(outs ACRegs:$dst), (ins ACRegs:$src), []>;
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
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def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
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ADDI_FM<0x9>, IsAsCheapAsAMove;
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def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
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def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
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def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
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def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
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def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
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def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
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SLTI_FM<0xa>;
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def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
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SLTI_FM<0xb>;
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def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
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ADDI_FM<0xc>;
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def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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ADDI_FM<0xd>;
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def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
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def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
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ADDI_FM<0xe>;
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def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
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def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>;
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def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
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def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
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def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
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def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
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def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
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def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
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def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
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def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
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def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
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def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
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def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>,
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ADD_FM<0, 0x21>;
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def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>,
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ADD_FM<0, 0x23>;
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def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
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ADD_FM<0x1c, 2>;
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def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
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def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
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def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
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def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
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def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
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ADD_FM<0, 0x24>;
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def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
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ADD_FM<0, 0x25>;
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def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
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ADD_FM<0, 0x26>;
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def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
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||||
|
||||
/// Shift Instructions
|
||||
def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
|
||||
@ -969,8 +977,10 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
|
||||
}
|
||||
|
||||
/// Multiply and Divide Instructions.
|
||||
def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>;
|
||||
def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>;
|
||||
def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
|
||||
MULT_FM<0, 0x18>;
|
||||
def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
|
||||
MULT_FM<0, 0x19>;
|
||||
def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>;
|
||||
def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>;
|
||||
def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
|
||||
@ -1329,3 +1339,6 @@ include "Mips16InstrInfo.td"
|
||||
include "MipsDSPInstrFormats.td"
|
||||
include "MipsDSPInstrInfo.td"
|
||||
|
||||
// Micromips
|
||||
include "MicroMipsInstrFormats.td"
|
||||
include "MicroMipsInstrInfo.td"
|
||||
|
||||
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Reference in New Issue
Block a user