From f54d912e32d19037391a59fc37336486b280187d Mon Sep 17 00:00:00 2001 From: Brian Gaeke Date: Tue, 22 Jun 2004 20:14:41 +0000 Subject: [PATCH] Add pseudo-registers and register class for 64-bit integer values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14332 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcRegisterInfo.cpp | 4 +-- lib/Target/Sparc/SparcRegisterInfo.td | 29 ++++++++++++++++++++++ lib/Target/SparcV8/SparcV8RegisterInfo.cpp | 4 +-- lib/Target/SparcV8/SparcV8RegisterInfo.td | 29 ++++++++++++++++++++++ 4 files changed, 62 insertions(+), 4 deletions(-) diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 67a67428e96..aa86e4859ce 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -131,8 +131,8 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { case Type::FloatTyID: return &FPRegsInstance; case Type::DoubleTyID: return &DFPRegsInstance; case Type::LongTyID: - case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); - default: assert(0 && "Invalid type to getClass!"); + case Type::ULongTyID: return &LongRegsInstance; + default: assert(0 && "Invalid type to getClass!"); case Type::BoolTyID: case Type::SByteTyID: case Type::UByteTyID: diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index d8d130ccf54..d424ebe6485 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -16,6 +16,10 @@ class Ri num> : Register { field bits<5> Num = num; } +// Rl - Slots in the integer register file for 64-bit integer values. +class Rl num> : Register { + field bits<5> Num = num; +} // Rf - 32-bit floating-point registers class Rf num> : Register { field bits<5> Num = num; @@ -40,6 +44,12 @@ let Namespace = "V8" in { def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; + // Aliases of the Ri registers used to hold 64-bit integer values. + def LG2 : Rl< 2>; def LG4 : Rl< 4>; def LG6 : Rl< 6>; + def LO0 : Rl< 8>; def LO2 : Rl<10>; def LO4 : Rl<12>; + def LL0 : Rl<16>; def LL2 : Rl<18>; def LL4 : Rl<20>; def LL6 : Rl<22>; + def LI0 : Rl<24>; def LI2 : Rl<26>; def LI4 : Rl<28>; + // Standard register aliases. def SP : Ri<14>; def FP : Ri<30>; @@ -82,6 +92,9 @@ def IntRegs : RegisterClass; + def FPRegs : RegisterClass; @@ -107,3 +120,19 @@ def : RegisterAliases; def : RegisterAliases; def : RegisterAliases; def : RegisterAliases; + +// Tell the register file generator that the long integer pseudo-registers +// alias the registers used for single-word integer values. +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp index 67a67428e96..aa86e4859ce 100644 --- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp @@ -131,8 +131,8 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { case Type::FloatTyID: return &FPRegsInstance; case Type::DoubleTyID: return &DFPRegsInstance; case Type::LongTyID: - case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); - default: assert(0 && "Invalid type to getClass!"); + case Type::ULongTyID: return &LongRegsInstance; + default: assert(0 && "Invalid type to getClass!"); case Type::BoolTyID: case Type::SByteTyID: case Type::UByteTyID: diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td index d8d130ccf54..d424ebe6485 100644 --- a/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -16,6 +16,10 @@ class Ri num> : Register { field bits<5> Num = num; } +// Rl - Slots in the integer register file for 64-bit integer values. +class Rl num> : Register { + field bits<5> Num = num; +} // Rf - 32-bit floating-point registers class Rf num> : Register { field bits<5> Num = num; @@ -40,6 +44,12 @@ let Namespace = "V8" in { def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; + // Aliases of the Ri registers used to hold 64-bit integer values. + def LG2 : Rl< 2>; def LG4 : Rl< 4>; def LG6 : Rl< 6>; + def LO0 : Rl< 8>; def LO2 : Rl<10>; def LO4 : Rl<12>; + def LL0 : Rl<16>; def LL2 : Rl<18>; def LL4 : Rl<20>; def LL6 : Rl<22>; + def LI0 : Rl<24>; def LI2 : Rl<26>; def LI4 : Rl<28>; + // Standard register aliases. def SP : Ri<14>; def FP : Ri<30>; @@ -82,6 +92,9 @@ def IntRegs : RegisterClass; + def FPRegs : RegisterClass; @@ -107,3 +120,19 @@ def : RegisterAliases; def : RegisterAliases; def : RegisterAliases; def : RegisterAliases; + +// Tell the register file generator that the long integer pseudo-registers +// alias the registers used for single-word integer values. +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases; +def : RegisterAliases;